Bootstrap capacitor charging circuit for GaN devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
1. A charging circuit comprising:
a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground referenced power supply to a floating power supply terminal, wherein the semiconductor circuit comprises an enhancement-mode transistor that includes a gate and a source connected to a common voltage potential.
2. The charging circuit of claim 1 wherein the semiconductor circuit is configured to be capable of operating with the floating power supply terminal at a voltage that is 20 volts or greater than a voltage of the ground referenced power supply.
3. The charging circuit of claim 1 wherein the drain of the enhancement-mode transistor is connected to the floating power supply terminal.
4. The charging circuit of claim 1 wherein the gate of the enhancement mode transistor is controlled by a gate drive circuit.
5. The charging circuit of claim 4 the drain of the enhancement mode transistor is connected to the floating power supply terminal.
6. The charging circuit of claim 1 wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising:
a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit; and
a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal.
7. The charging circuit of claim 6 wherein the second floating power supply terminal is a switch node of the half bridge circuit.
8. The charging circuit of claim 6 wherein a capacitor is connected between the floating power supply terminal and the second floating power supply terminal.
9. The charging circuit of claim 6 wherein the semiconductor circuit comprises a second enhancement-mode transistor including a gate that is controlled by a gate drive circuit; and
wherein the gate drive circuit is configured such that it provides an output voltage that is in phase with the low side gate signal.
10. The charging circuit of claim 9 further comprising a delay circuit configured to turn on the second enhancement-mode transistor after the low side GaN-based transistor turns on.
11. The charging circuit of claim 9 further comprising a delay circuit configured to turn off the enhancement-mode transistor before the low side GaN-based transistor turns off.
12. An electronic power conversion component comprising:
a package base;
one or more GaN-based dies secured to the package base and including a charging circuit comprising:
a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground referenced power supply to a floating power supply terminal, wherein the semiconductor circuit comprises an enhancement-mode transistor that includes a gate and a source connected to a common voltage potential.
13. An electronic power conversion component comprising:
a package base; and
one or more GaN-based dies secured to the package base and including a charging circuit comprising:
a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground referenced power supply to a floating power supply terminal, wherein the semiconductor circuit includes an enhancement mode transistor having a drain that is connected to a source of a depletion mode transistor, and wherein a drain of the depletion mode transistor is connected to the floating power supply terminal.
14. A charging circuit comprising:
a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground referenced power supply to a floating power supply terminal, wherein the semiconductor circuit comprises an enhancement mode transistor that includes a gate that is controlled by a gate drive circuit and a drain connected to the floating power supply terminal and to a source of a depletion mode transistor, and wherein a drain of the depletion mode transistor is connected to the floating power supply terminal.
15. The charging circuit of claim 14 wherein the semiconductor circuit is configured to be capable of operating with the floating power supply terminal at a voltage that is 20 volts or greater than a voltage of the ground referenced power supply.
16. The charging circuit of claim 14 wherein a gate of the depletion mode transistor is connected to the ground referenced power supply.
17. The charging circuit of claim 14 wherein a gate of the depletion mode transistor is connected to ground.
18. The charging circuit of claim 14 wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising:
a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit; and
a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal.
19. The charging circuit of claim 18 wherein the second floating power supply terminal is a switch node of the half bridge circuit.
20. The charging circuit of claim 18 wherein a capacitor is connected between the floating power supply terminal and the second floating power supply terminal.
21. The charging circuit of claim 18 wherein the gate drive circuit is configured such that it provides an output voltage that is in phase with the low side gate signal.
22. The charging circuit of claim 21 further comprising a delay circuit configured to turn on the enhancement-mode transistor after the low side GaN-based transistor turns on.
23. The charging circuit of claim 22 further comprising a delay circuit configured to turn off the enhancement-mode transistor before the low side GaN-based transistor turns off.