Phase alignment architecture for ultra high-speed data path
View Patent ↗A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.
1. A system comprising:
a clock driver comprising a transmit clock output;
a clock divider comprising:
an inphase clock output; and
a quadrature clock output;
where the clock divider is configured to accept the transmit clock output and drive the inphase clock output and quadrature clock output according to the transmit clock output; and
a phase detector comprising:
a phase detector output;
a phase selection circuit configured to determine a selected phase between the inphase clock output and the quadrature clock output;
a sampling circuit configured to obtain a clock sample from the transmit clock output responsive to the selected phase; and
a comparator configured to output a digital representation of the clock sample on the phase detector output.
2. The system of claim 1 , further comprising:
processing circuitry configured to accept the phase detector output and determine a phase correction.
3. The system of claim 2 , where the phase correction comprises a phase correction to the inphase clock output, the quadrature clock output, or both, with respect to the transmit clock output.
4. The system of claim 2 , further comprising:
a phase interpolator in communication with the inphase clock output and the processing circuitry, the phase interpolator comprising a phase correction input responsive to the phase correction.
5. The system of claim 2 , further comprising:
a phase interpolator in communication with the quadrature clock output and the processing circuitry, the phase interpolator comprising a phase correction input responsive to the phase correction.
6. The system of claim 1 , where the sampling circuit comprises:
a first clock sampler in series with a second clock sampler.
7. The system of claim 2 , where:
the comparator is further configured to output a digital representation of the clock sample using a comparison threshold chosen for input compatibility with the processing circuitry.
8. The system of claim 2 , where the processing circuitry comprises a phase selection output that specifies the selected phase for the phase selection circuit.
9. A method comprising:
generating a transmit clock output;
dividing the transmit clock output to obtain an inphase clock output and a quadrature clock output;
responding to a phase selection input to determine a selected phase between the inphase clock output and the quadrature clock output;
sampling the transmit clock output with the selected phase to obtain a clock sample; and
outputting a digital representation of the clock sample on a phase detector output.
10. The method of claim 9 , further comprising:
determining a phase correction responsive to the phase detector output.
11. The method of claim 10 , where determining comprises:
determining a phase correction to the inphase clock output, the quadrature clock output, or both, with respect to the transmit clock output.
12. The method of claim 10 , further comprising:
adjusting phase of the inphase clock output responsive to receiving the phase correction.
13. The method of claim 10 , further comprising:
adjusting phase of the quadrature clock output responsive to receiving the phase correction.
14. The method of claim 9 , where sampling comprises:
two stage sampling comprising sampling with a first clock sampler in series with a second clock sampler.
15. The method of claim 10 , further comprising:
adjusting the digital representation for input compatibility with processing circuitry that determines the phase correction.
16. The method of claim 15 , further comprising:
receiving a phase selection output from the processing circuitry that specifies the selected phase.
17. A system comprising:
a clock driver comprising a transmit clock output;
a clock divider comprising:
an inphase clock output; and
a quadrature clock output;
where the clock divider is configured to:
accept the transmit clock output; and
drive the inphase clock output and quadrature clock output responsive to the transmit clock output;
an inphase phase interpolator in communication with the inphase clock output, the inphase phase interpolator comprising a phase adjusted inphase clock output;
a quadrature phase interpolator in communication with the quadrature clock output, the quadrature phase interpolator comprising a phase adjusted quadrature clock output; and
transmit stream circuitry comprising:
an inphase data selector driven by the adjusted inphase clock output;
a quadrature data selector driven by the adjusted quadrature clock output; and
a transmit data selector configured to combine transmit data received from the inphase data selector and the quadrature data selector into a transmit stream according to the transmit clock output.
18. The system of claim 17 , further comprising:
a phase detector comprising:
a phase detector output;
a phase selection circuit configured to determine a selected phase between the inphase clock output and the quadrature clock output; and
a sampling circuit configured to obtain timing samples from the transmit clock output responsive to the selected phase.
19. The system of claim 18 , further comprising:
processing circuitry configured to:
accept the timing samples;
determine an inphase clock phase correction over time responsive to the timing samples; and
determine a quadrature clock phase correction over time responsive to the timing samples.
20. The system of claim 19 , where:
the inphase phase interpolator is in communication with the processing circuitry and configured to:
receive the inphase clock phase correction; and
responsively generate the phase adjusted inphase clock output; and
the quadrature phase interpolator is in communication with the processing circuitry and configured to:
receive the quadrature clock phase correction; and
responsively generate the phase adjusted quadrature clock output.