Protection of data stored in an integrated circuit

1. A method, comprising:

sampling, using a sampling circuit, a series of bits output by a logic circuit of an integrated circuit, the logic circuit including a plurality of ring oscillators having outputs XORed together to generate the series of bits;

generating, using the sampling circuit, an indication of a proportion of the series of bits in a first state;

generating, using the sampling circuit, an indication of detection of a cold-boot attack based on the generated indication of the proportion of the series of bits in the first state; and

restricting access to the integrated circuit in response to the indication of detection of a cold-boot attack indicating a cold-boot attack, wherein;

the generating the indication of the proportion comprises counting a number of bits in the first state and the generating the indication of detection of the cold-boot attack comprises determining whether the number of bits in the first state is within a range of values; and

the range of values is determined by statistical analysis in a training phase during which the integrated circuit is repeatedly switched down and up.

2. The method of claim 1 wherein said range of values is determined by statistical analysis in a training phase during which the integrated circuit is operated in a normal temperature range.

3. The method of claim 1 wherein the generating the indication of detection of the cold-boot attack comprises comparing the number of bits in the first state to one or more threshold values.

4. The method of claim 3 wherein the first state is a one state.

5. The method of claim 1 , comprising periodically repeating the sampling, the generating of the indication of the proportion and the generating of the indication of detection of a cold-boot attack.

6. A device, comprising:

a logic circuit having a plurality of ring oscillators, wherein the logic circuit, in operation, XORs outputs of the plurality of ring oscillators together, generating an output signal; and

sampling circuitry, which, in operation:

samples the output signal generated by the logic circuit;

generates an indication of a proportion of bits in the sampled output signal in a first state;

generates an indication of detection of a cold-boot attack based on the generated indication of the proportion of the bits in the first state; and

generates one or more signals to restrict access to the device in response to the indication of detection of a cold-boot attack indicating a cold-boot attack, wherein:

the sampling circuitry is configured to count a number of bits in the sampled output signal in the first state and to generate the indication of detection of the cold-boot attack based on whether the counted number of bits is within a range of values; and

the range of values is determined by statistical analysis in a training phase during which the integrated circuit is repeatedly switched down and up.

7. The device of claim 6 wherein the device is an integrated circuit.

8. The device of claim 6 wherein said range of values is determined by statistical analysis in a training phase during which the integrated circuit is operated in a normal temperature range.

9. The device of claim 6 wherein the sampling circuitry is configured to compare the counted number of bits in the first state to one or more threshold values.

10. The device of claim 6 wherein the sampling circuitry is configured to periodically repeat the sampling, the generating of the indication of the proportion and the generating of the indication of detection of a cold-boot attack.

11. The device of claim 6 comprising a flip-flop configured to sample the output signal of the logic circuit.

12. The device of claim 6 , comprising a non-volatile memory having said range of values stored therein.

13. The device of claim 7 , comprising a volatile memory configured to store information.

14. A system, comprising:

a processor;

a random access memory; and

cold-boot attack detection circuitry, including:

a logic circuit having a plurality of ring oscillators, wherein the logic circuit, in operation, XORs outputs of the plurality of ring oscillators together, generating an output signal of the logic circuit; and

sampling circuitry configured to:

sample the output signal generated by the logic circuit;

generate an indication of a proportion of bits in the sampled output signal in a first state;

generate an indication of a cold-boot attack based on the generated indication of the proportion of the bits in the first state; and

generate one or more signals to restrict access to at least one of the processor and the memory in response to the indication of detection of a cold-boot attack indicating a cold-boot attack, wherein:

the generating the indication of the proportion comprises counting a number of bits in the first state and the generating the indication of detection of the cold-boot attack comprises determining whether the number of bits in the first state is within a range of values; and

the range of values is determined by statistical analysis in a training phase during which the integrated circuit is repeatedly switched down and up.

15. The system of claim 14 comprising an integrated circuit including the cold-boot attack detection circuitry.

16. The system of claim 14 wherein the sampling circuitry is configured to periodically repeat the sampling, the generating of the indication of the proportion and the generating of the indication of detection of a cold-boot attack.

17. A method, comprising:

sampling, using a sampling circuit, an output signal of a logic circuit of an integrated circuit, the logic circuit including a plurality of ring oscillators having outputs XORed together;

generating, using the sampling circuit, an indication of a shape of the output signal of the logic circuit;

generating, using the sampling circuit, an indication of detection of a cold-boot attack based on the generated indication of the shape of the output signal; and

restricting access to the integrated circuit in response to the indication of detection of a cold-boot attack indicating a cold-boot attack, wherein the method comprises training the sampling circuit in a training phase during which the integrated circuit is repeatedly switched down and up.

18. The method of claim 17 , comprising training the sampling circuit in a training phase during which the integrated circuit is operated normally.