Protection of data stored in a volatile memory
A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.
1. A method, comprising:
transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit; and
periodically,
switching down and switching up the first volatile memory;
generating an indication of a number of switched bits in the first volatile memory;
comparing the indication of the number of switched bits to one or more thresholds indicative of whether a cold-boot attack is occurring; and
detecting an occurrence of a cold-boot attack based on the comparison of the indication of the number of switched bits to the one or more thresholds indicative of whether a cold-boot attack is occurring.
2. The method of claim 1 wherein the pattern is reloaded into the first volatile memory before each switching down.
3. The method of claim 1 wherein the pattern is selected so that said number of bits which switch state varies according to the integrated circuit temperature.
4. The method of claim 1 wherein the one or more thresholds define a range of values and the detecting the cold-boot attack comprises determining whether the indication of the number of switched bits is within the range of values.
5. The method of claim 4 wherein said range of values is determined by statistical analysis of states taken by the bits of the first volatile memory in successive switch up operations during a training phase.
6. The method of claim 1 wherein the generating the indication of the number of switched bits comprises counting at least one of:
a number of bits in a first state; and
a number of bits in a second state different from the first state.
7. The method of claim 6 wherein the comparing the indication of the number of switched bits to one or more thresholds comprises at least one of:
comparing the number of bits in the first state to one or more threshold values; and
comparing the number of bits in the second state to one or more threshold values.
8. The method of claim 1 wherein the integrated circuit comprises a second volatile memory separate from the first volatile memory and the first volatile memory is switched up and switched down independent of the second volatile memory.
9. The method of claim 1 , comprising:
implementing one or more countermeasures in response to detection of a cold-boot attack.
10. A device, comprising:
a first volatile memory;
a non-volatile memory; and
cold-boot detection circuitry configured to:
transfer a pattern stored in the non-volatile memory to the first volatile memory; and
periodically,
switch down and switch up the first volatile memory;
generate an indication of a number of switched bits in the first volatile memory;
compare the indication of the number of switched bits to one or more thresholds indicative of whether a cold-boot attack is occurring; and
detect a cold-boot attack based on the comparison of the indication of the number of switched bits to the one or more thresholds indicative of whether a cold-boot attack is occurring.
11. The device of claim 10 wherein the pattern is reloaded into the first volatile memory before each switching down.
12. The device of claim 10 wherein the pattern is selected so that said number of bits which switch state is an indication of a temperature of the device.
13. The device of claim 10 wherein the cold-boot attack detection circuitry is configured to determine whether the indication of the number of switched bits is within a range of values.
14. The device of claim 13 wherein the range of values is determined by statistical analysis of states taken by the bits of the first volatile memory in successive switch up operations during a training phase.
15. The device of claim 10 wherein the cold-boot detection circuitry comprises a counter.
16. The device of claim 15 wherein the cold-boot detection circuitry is configured to count at least one of:
a number of bits in a first state; and
a number of bits in a second state different from the first state.
17. The device of claim 10 , comprising an integrated circuit including the first volatile memory, the non-volatile memory and the cold-boot detection circuitry.
18. The device of claim 17 wherein the integrated circuit includes a second volatile memory different from the first volatile memory and the second volatile memory is configured to, in operation, store protected data.
19. The device of claim 10 , comprising:
a second volatile memory separate from the first volatile memory, wherein the cold-boot detection circuitry switches down and switches up the first volatile memory independent of the second volatile memory.
20. The device of claim 10 wherein the cold-boot detection circuitry implements one or more countermeasures in response to detection of a cold-boot attack.
21. A system, comprising:
a processing unit;
a first volatile memory;
a non-volatile memory; and
cold-boot detection circuitry configured to:
transfer a pattern stored in the non-volatile memory to the first volatile memory; and
periodically,
switch down and switch up the first volatile memory;
generate an indication of a number of switched bits in the first volatile memory;
compare the indication of the number of switch bits to one or more thresholds indicative of whether a cold-boot attack is occurring; and
detect a cold-boot attack based on the comparison of the indication of the number of switched bits to the one or more thresholds indicative of whether a cold-boot attack is occurring.
22. The system of claim 21 wherein the cold-boot attack detection circuitry is configured to determine whether the indication of the number of switched bits is within a range of values.
23. The system of claim 22 wherein the range of values is determined by statistical analysis of states taken by the bits of the first volatile memory in successive switch up operations during a training phase.
24. The system of claim 21 wherein the cold-boot detection circuitry comprises a counter.
25. The system of claim 21 , comprising an integrated circuit including the first volatile memory, the non-volatile memory and the cold-boot detection circuitry.
26. The system of claim 25 wherein the integrated circuit includes a second volatile memory different from the first volatile memory.