Notch filter for ripple reduction
A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.
1. A circuit comprising:
an input chopper receiving an input signal;
an amplifier receiving a first signal corresponding to an output of the input chopper;
an output chopper, synchronized with the input chopper, receiving a second signal corresponding to an output of the amplifier, the output chopper comprising a first set of switches controlled by at least clocked phase 1 and phase 2 control signals at a chopping frequency, the output chopper outputting a third signal containing chopping ripple at the chopping frequency; and
a notch filter coupled to receive the output of the output chopper, the notch filter comprising a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor,
wherein the sampling capacitor is directly coupled to an output of the output chopper with no switches therebetween,
wherein the second set of switches is temporarily closed during each output chopper switch cycle to connect the sampling capacitor to the hold capacitor, pursuant to a phase 3 control signal at the chopper frequency, to transfer charge from the sampling capacitor to the hold capacitor at least once per switching cycle of the output chopper, wherein the hold capacitor is isolated from the output chopper during times when the second set of switches is open, such that the chopping ripple from the output chopper is not transferred to the hold capacitor.
2. The circuit of claim 1 wherein the clocked phase 1 and phase 2 control signals for the output chopper have a non-overlapping time, and wherein the phase 3 control signal for the notch filter occurs during the non-overlapping time.
3. The circuit of claim 1 wherein the phase 3 control signal occurs at a same time during each output chopper switching cycle.
4. The circuit of claim 1 wherein the output of the input chopper is a first differential signal, the output of the amplifier is a second differential signal, the output of the output chopper is a third differential signal, and the output of the notch filter is a fourth differential signal.
5. The circuit of claim 4 further comprising a zeroing switch coupled across differential outputs of the amplifier, wherein the zeroing switch is controlled by the same phase 3 control signal used to control the second set of switches.
6. The circuit of claim 4 further comprising a zeroing switch coupled across differential outputs of the amplifier, wherein the zeroing switch is controlled by a phase 4 control signal that occurs at least once per output chopper switching cycle.
7. The circuit of claim 6 wherein the phase 4 control signal occurs twice per output chopper switching cycle.
8. The circuit of claim 4 further comprising a zeroing switch coupled across differential outputs of the output chopper, wherein the zeroing switch is controlled by the same phase 3 control signal used to control the second set of switches.
9. The circuit of claim 8 further comprising a third set of switches between the zeroing switch and the sampling capacitor, wherein the third set of switches is controlled by a phase 4 control signal that is opposite to the phase 3 control signal.
10. The circuit of claim 4 further comprising a differential amplifier coupled to receive a voltage across the hold capacitor.
11. The circuit of claim 1 wherein the second set of switches comprises a first switch selectively coupling a first terminal of the sampling capacitor to a first terminal of the hold capacitor, and a second switch, having the same state as the first switch, selectively coupling a second terminal of the sampling capacitor to a second terminal of the hold capacitor.
12. The circuit of claim 1 wherein the first set of switches in the output chopper comprises four switches.
13. The circuit of claim 1 wherein all switches are transistor switches.
14. The circuit of claim 1 wherein the amplifier is directly connected to an output of the input chopper, and wherein the output chopper is directly connected to an output of the amplifier.
15. The circuit of claim 1 wherein the chopping frequency is a fixed frequency.
16. A method for generating a signal and reducing ripple in the signal comprising:
receiving an input signal by an input chopper;
receiving a first signal, corresponding to an output of the input chopper, by an amplifier;
receiving a second signal, corresponding to an output of the amplifier, by an output chopper synchronized with the input chopper, the output chopper comprising a first set of switches controlled by at least clocked phase 1 and phase 2 control signals at a chopping frequency, the output chopper outputting a third signal containing chopping ripple at the chopping frequency;
receiving the output of the output chopper by a notch filter, the notch filter comprising a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor,
wherein the second set of switches is temporarily closed during each output chopper switch cycle to connect the sampling capacitor to the hold capacitor, pursuant to a phase 3 control signal at the chopper frequency, to transfer charge from the sampling capacitor to the hold capacitor at least once per switching cycle of the output chopper, wherein the hold capacitor is isolated from the output chopper during times when the second set of switches is open such that the chopping ripple from the output chopper is not transferred to the hold capacitor; and
wherein the output of the amplifier is a first differential output on first differential output terminals of the amplifier, and wherein the output of the output chopper is a second differential output on second differential output terminals of the output chopper, the method further comprising shorting either the first differential output terminals of the amplifier or the second differential output terminals of the output chopper together at least once per output chopper switching cycle.
17. The method of claim 16 further comprising shorting the first differential output terminals at least once per output chopper switching cycle.
18. The method of claim 17 wherein the shorting is performed by a zeroing switch coupled across the first differential output terminals of the amplifier.
19. The method of claim 17 wherein the shorting is performed by a zeroing switch coupled across the second differential output terminals of the output chopper.
20. The method of claim 17 wherein the shorting is performed by closing the first set of switches in the output chopper.