Apparatus and method for detecting and mitigating bit-line opens in flash memory
Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.
1. A method comprising:
performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword;
decoding the first codeword;
determining whether the decoding failed;
performing a second read from the portion of the non-volatile memory when it is determined that the decoding failed, the second read to provide a second codeword separate from the first codeword;
decoding the second codeword with an errors-and-erasures decoding process; and
identifying a location of an open circuit in response to performing the second read.
2. The method claim 1 comprising:
storing the location of the open circuit.
3. The method of claim 1 , wherein performing the first read comprises:
applying a read voltage to a selected word-line; and
applying a pass voltage to all other word-lines in the portion of the non-volatile memory.
4. The method of claim 3 , wherein performing the second read comprises:
applying the pass voltage to the selected word-line.
5. The method of claim 1 , wherein determining whether the decoding failed comprises:
determining whether a number of soft errors, associated with the decoding, exceeds a threshold.
6. The method of claim 1 , wherein the non-volatile memory includes a NAND memory.
7. The method of claim 1 , wherein decoding the first and second codewords is performed by one of:
a Low-Density Parity-Check Code (LDPC) decoder; or
a Reed-Solomon decoder.
8. The method of claim 1 , wherein the first and second codewords are one of:
Low-Density Parity-Check Codes (LDPCs); or
Reed-Solomon codes.
9. The method of claim 1 , wherein the errors-and-erasures decoding process comprises setting a Log Likelihood Ratio (LLR) for erasures to zero.
10. An apparatus comprising:
read circuitry to perform a first read from a portion of a non-volatile memory, the first read to provide a first codeword;
a decoder to perform a decoder operation to decode the first codeword;
one or more circuitries to determine whether the decoder operation failed;
wherein the read circuitry is to perform a second read from the portion of the non-volatile memory when it is determined that the decoder operation failed, the second read to provide a second codeword separate from the first codeword, and wherein the decoder is to decode the second codeword with an errors-and-erasures decoding process; and
logic to identity a location of an open circuit in response to the read circuitry to perform the second read.
11. The apparatus of claim 10 , wherein the read circuitry is to apply:
a read voltage to a selected word-line to perform the first read; and
a pass voltage to all other word-lines in the portion of the non-volatile memory.
12. The apparatus of claim 11 , wherein the read circuitry is to perform the second read by applying the pass voltage to the selected word-line.
13. The apparatus of claim 10 , wherein the decoder is one of:
a Low-Density Parity-Check Code (LDPC) decoder; or
a Reed-Solomon decoder.
14. The apparatus of claim 10 , wherein the non-volatile memory includes a NAND memory.
15. The apparatus of claim 10 , wherein the decoder is to determine whether the decoder operation failed by comparing a number of soft errors, associated with the decoder operation, against a threshold.
16. The apparatus of claim 10 comprises a storage unit to store the location of the open circuit in the non-volatile memory in response to the logic determining that the decoder operation failed.
17. A system comprising:
a processor;
a non-volatile memory;
a memory controller coupled to the non-volatile memory, the memory controller including:
read logic to perform a first read from a portion of the non-volatile memory, the first read to provide a first codeword;
a decoder to perform a decoder operation to decode the first codeword; and
logic to determine whether the decoder operation failed; wherein the read logic is to perform a second read from the portion of the non-volatile memory when it is determined that the decoder operation failed, the second read to provide a second codeword separate from the first codeword, and wherein the decoder is to decode the second codeword with an errors-and-erasures decoding process; and
logic to identity a location of an open circuit in response to the read circuitry to perform the second read; and
a wireless interface to allow the processor to communicate with another device.
18. The system of claim 17 , wherein the read logic is to apply:
a read voltage to a selected word-line to perform the first read; and
a pass voltage to all other word-lines in the portion of the non-volatile memory.
19. The system of claim 18 , wherein the read logic is to perform the second read by applying the pass voltage to the selected word-line.
20. The system of claim 17 , wherein the non-volatile memory includes a NAND memory.