IP Library Granted Patent US 10,025,535
Granted Patent B2
US 10,025,535 · App. 14/671,663 · Granted Jul 17, 2018

Measurement and reporting of the latency of input and output operations by a solid state drive to a host

Inventors: Robert E. Frickey, III (Sacramento, CA); Ye Zhang (Shanghai, CN)
Assignee: INTEL CORPORATION
G06F3/0679G06F3/061G06F3/0653G06F3/0688
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Quick Facts
Patent No.
US 10,025,535
App. No.
14/671,663
Granted
Jul 17, 2018
Kind
B2
Abstract

Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.

Claims (44)

1. A method for measuring latency of a solid state drive (SSD), the method comprising:

initializing, by the SSD, a latency profile comprising latency intervals and corresponding number of I/O operations that have latencies falling within the latency intervals and initially setting number of I/O operations for each latency interval to zero;

in response to receiving one or more input/output (I/O) operations by the SSD from a host, measuring, by a logic included in a controller within the SSD, one or more latencies of the one or more input/output (I/O) operations received from the host, wherein the logic measures a latency of an I/O operation that comprises a write I/O operation received from the host by computing a time difference between a time of receiving at the SSD, a last byte of data to be written to the SSD from the host, and a time at which a last byte of data of a response to the write I/O operation is sent by the SSD to the host to communicate to the host that data corresponding to the write I/O operation has been written to one or more non-volatile memory chips of the SSD;

for each I/O operation of the one or more I/O operations received by the SSD from the host, determining a latency interval within which the latency of the I/O operation falls and incrementing the number of I/O operations for the latency interval by one; and

in response to determining that that host has requested the latency profile, transmitting from the SSD the latency profile to the host, wherein all measurements of the one or more latencies are performed in the SSD and no measurements of the one or more latencies are performed in the host, and wherein by measuring the one or more latencies in the SSD and not in the host, the measurements of the one or more latencies do not include delays introduced by extraneous effects of processes that execute in the host.

2. The method of claim 1 , the method further comprising:

recording, by the SSD, a first time at which the I/O operation is received from the host;

recording, by the SSD, a second time at which the SSD transmits a response to the I/O operation to the host; and

determining a latency of the I/O operation to be a time duration between the second time and the first time.

3. The method of claim 1 , wherein the logic measures a latency of a read I/O operation received from the host by computing a time difference between a time of receiving at the SSD, a last byte of the read I/O operation from the host, and a time at which a last byte of data of a response to the read I/O operation is sent to the host by the SSD.

4. The method of claim 3 , wherein an internal clock of the SSD is used to record timestamps for computing time differences.

5. The method of claim 4 , wherein the one of more latencies are unaffected by delays in the host and coupling elements between the host and the SSD.

6. The method of claim 1 , wherein the SSD is configured to communicate with the host over a network, and wherein the one of more latencies are unaffected by delays in the network.

7. An apparatus, comprising:

a plurality of non-volatile memory chips; and

a controller coupled to the plurality of non-volatile memory chips, wherein logic included in the controller is operable to:

initialize a latency profile comprising latency intervals and corresponding number of I/O operations that have latencies falling within the latency intervals and initially set a number of I/O operations for each latency interval to zero;

in response to receiving one or more input/output (I/O) operations from a host, measure one or more latencies of the one or more input/output (I/O) operations received from the host, wherein the logic measures a latency of an I/O operation that comprises a write I/O operation received from the host by computing a time difference between a time of receiving a last byte of data to be written from the host, and a time at which a last byte of data of a response to the write I/O operation is sent to the host to communicate to the host that data corresponding to the write I/O operation has been written to one or more of the plurality of non-volatile memory chips;

for each I/O operation of the one or more I/O operations received from the host, determine a latency interval within which the latency of the I/O operation falls and increment the number of I/O operations for the latency interval by one; and

in response to determining that that host has requested the latency profile, transmit the latency profile to the host, wherein all measurements of the one or more latencies are performed in the apparatus and no measurements of the one or more latencies are performed in the host, and wherein by measuring the one or more latencies in the apparatus and not in the host, the measurements of the one or more latencies do not include delays introduced by extraneous effects of processes that execute in the host.

8. The apparatus of claim 7 , wherein the logic included in the controller is further operable to:

record a first time at which the I/O operation is received from the host;

record a second time at which the apparatus transmits a response to the I/O operation to the host; and

determine a latency of the I/O operation to be a time duration between the second time and the first time.

9. The apparatus of claim 7 , wherein the logic is further operable to measure a latency of a read I/O operation received from the host by computing a time difference between a time of receiving at the apparatus, a last byte of the read I/O operation from the host, and a time at which a last byte of data of a response to the read I/O operation is sent to the host by the apparatus.

10. The apparatus of claim 9 , wherein an internal clock of the apparatus is used to record timestamps for computing time differences.

11. The apparatus of claim 10 , wherein the one of more latencies are unaffected by delays in the host and coupling elements between the host and the apparatus.

12. The apparatus of claim 7 , wherein the apparatus is configured to communicate with the host over a network, and wherein the one of more latencies are unaffected by delays in the network.

13. A system, comprising:

a solid state drive (SSD) comprising a plurality of non-volatile memory chips;

a display; and

a processor coupled to the solid state drive and the display, wherein logic included in a controller within the SSD is operable to:

initialize, by the SSD, a latency profile comprising latency intervals and corresponding number of I/O operations that have latencies falling within the latency intervals and initially set number of I/O operations for each latency interval to zero;

in response to receiving one or more input/output (I/O) operations by the SSD from a host, measure, by a logic included in a controller within the SSD, one or more latencies of the one or more input/output (I/O) operations received from the host, wherein the logic measures a latency of an I/O operation that comprises a write I/O operation received from the host by computing a time difference between a time of receiving at the SSD, a last byte of data to be written to the SSD from the host, and a time at which a last byte of data of a response to the write I/O operation is sent by the SSD to the host to communicate to the host that data corresponding to the write I/O operation has been written to one or more non-volatile memory chips of the SSD;

for each I/O operation of the one or more I/O operations received by the SSD from the host, determine a latency interval within which the latency of the I/O operation falls and increment the number of I/O operations for the latency interval by one; and

in response to determining that that host has requested the latency profile, transmit from the SSD the latency profile to the host, wherein all measurements of the one or more latencies are performed in the SSD and no measurements of the one or more latencies are performed in the host, and wherein by measuring the one or more latencies in the SSD and not in the host, the measurements of the one or more latencies do not include delays introduced by extraneous effects of processes that execute in the host.

14. The system of claim 13 , wherein the host is included in the system and coupled to the SSD, and the processor is included in the host, wherein the logic included in the SSD is further operable to:

record a first time at which the I/O operation is received from the host;

record a second time at which the SSD transmits a response to the I/O operation to the host; and

determine a latency of the I/O operation to be a time duration between the second time and the first time.

15. The system of claim 13 , wherein the logic is further operable to measure a latency of a read I/O operation received from the host by computing a time difference between a time of receiving at the SSD, a last byte of the read I/O operation from the host, and a time at which a last byte of data of a response to the read I/O operation is sent to the host by the SSD.

16. The system of claim 15 , wherein an internal clock of the SSD is used to record timestamps for computing time differences.

17. The system of claim 16 , wherein the one of more latencies are unaffected by delays in the host and coupling elements between the host and the SSD.

18. The system of claim 13 , wherein the SSD is configured to communicate with the host over a network, and wherein the one of more latencies are unaffected by delays in the network.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2015
From: FRICKEY, ROBERT E., III; ZHANG, YE
To: INTEL CORPORATION
Reel/Frame 035451/0589 →
Continuity (1)
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