Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
1. A method of improving a bandwidth response of a programmable gain amplifier (PGA) loaded by a plurality of analog to digital convertors (ADC's) comprising the steps of:
coupling a differential output of said PGA to a differential interconnect;
coupling a differential input of each said plurality of ADC's to said differential interconnect; and
coupling a negative-capacitance circuit to said differential interconnect,
wherein said negative-capacitance circuit comprises:
a first transistor cross-coupled to a second transistor with a capacitor coupling their sources together;
a first current source coupled to said first transistor; and
a second current source coupled to said second transistor.
2. The method of claim 1 , wherein
said first current source and said second current source are both controlled by one control circuit.
3. The method of claim 1 , wherein
said first current source and said second current source have substantially equivalent characteristics.
4. The method of claim 1 , wherein
said first current source and said second current source are each controlled by separate control circuits.
5. The method of claim 1 , further comprising the steps of:
adjusting a current of at least one of said first current source and said second current source to improve said bandwidth response of said PGA loaded by said plurality of ADC's.
6. The method of claim 5 , wherein
said current of said first and said second current source is controlled by a digital adjustment or an analog adjustment in a control circuit.
7. The method of claim 1 , wherein
said differential output of said PGA is either a differential in-phase analog signal or a differential quadrature-phase analog signal.
8. An apparatus comprising:
a differential amplifier configured to provide a differential analog signal on a first node and a second node;
a first transistor coupling said first node to a first current node;
a second transistor coupling said second node to a second current node,
wherein said first transistor is cross coupled to said second transistor;
a third transistor coupling said first current node to a supply voltage;
a fourth transistor coupling said second current node to said supply voltage;
a capacitor coupling said first current node to said second current node; and
gates of said third and fourth transistors coupled to a control circuit,
wherein said output of said control circuit is configured to control a current in each of said third and said fourth transistors.
9. The apparatus of claim 8 , further comprising:
a plurality of comparators coupled to said first and second node.
10. The apparatus of claim 8 , wherein
said differential analog signal is either a differential in-phase analog signal or a differential quadrature-phase analog signal.
11. The apparatus of claim 8 , further comprising:
a fifth transistor coupling said control circuit to said gates of said third and fourth transistors,
wherein said control circuit is analog controlled, digitally controlled, or a combination of the two.
12. The apparatus of claim 8 , wherein
said third transistor is matched to said fourth transistor.
13. The apparatus of claim 12 , wherein
said current in said third transistor substantially equals said current in said fourth transistor.
14. The apparatus of claim 8 , wherein
said differential amplifier is a programmable gain amplifier.
15. A method of improving a bandwidth response of a programmable gain amplifier (PGA) loaded by a plurality of analog to digital convertors (ADC's) comprising the steps of:
coupling a differential output of said PGA to a differential interconnect;
coupling a differential input of each said plurality of ADC's to said differential interconnect;
coupling a negative-capacitance circuit to said differential interconnect;
sensing a transition of a differential analog signal from said differential output of said PGA by said negative-capacitance circuit; and
shorting a time period to perform a transfer of said differential analog signal on said differential interconnect due to a response of said negative-capacitance circuit.
16. The method of claim 15 , wherein
said negative-capacitance circuit comprises:
a first transistor cross-coupled to a second transistor with a capacitor coupling their sources together;
a first current source coupled to said first transistor; and
a second current source coupled to said second transistor.
17. The method of claim 16 , wherein
said first current source and said second current source are both controlled by one control circuit.
18. The method of claim 16 , wherein
said first current source and said second current source have substantially equivalent characteristics.
19. The method of claim 16 , further comprising the steps of:
adjusting a current of said first and said second current source to further improve said bandwidth response of said PGA.
20. The method of claim 19 , wherein
said current of said first and said second current source is controlled by a digital adjustment or an analog adjustment of a control circuit.