Semiconductor isolation structure
The invention relates to a semiconductor isolation structure. More particularly, the present invention relates to a semiconductor isolation structure suitable for providing high voltage isolation. Embodiments disclosed include a semiconductor structure ( 10 ) comprising: a first semiconductor region (R 1 ), a second semiconductor region (R 2 ) within the first semiconductor region (R 1 ), and a voltage isolator ( 11 ) separating the first and second semiconductor regions (R 1 , R 2 ), the voltage isolator ( 11 ) comprising: a nested series of insulating regions (T 1 , T 2 ) around the perimeter of the second semiconductor region (R 2 ), an intermediate semiconductor region (I 1 , I 2 ) between each adjacent pair of nested insulating regions (T 1 , T 2 ), and a voltage control device ( 12 ) comprising a conducting element (D 1 -D 3 ) connected to at least one intermediate semiconductor region (I 1 , I 2 ) in parallel with the at least one insulating region (T 1 , T 2 ), so as to control a voltage across the at least one insulating region (T 1 , T 2 ).
1. A semiconductor structure comprising:
a first semiconductor region,
a second semiconductor region within the first semiconductor region, and
a voltage isolator separating the first and second semiconductor region, the voltage isolator comprising:
a nested series of insulating regions around the perimeter of the second semiconductor region,
an intermediate semiconductor region between each adjacent pair of nested insulating regions, and
a voltage control device comprising a conducting element connected to at least one intermediate semiconductor region in parallel with the at least one insulating region, so as to control a voltage across the at least one insulating region.
2. The structure of claim 1 , wherein the voltage control device comprises a conducting element connected in parallel with each insulating region, so as to control the voltage across each insulating region.
3. The structure of claim 2 , wherein the voltage control device comprises a plurality of conducting elements connected in series, each conducting element being connected in parallel with a corresponding insulating region, the voltage control device being connected at a first location to the first region, at a second location to the second region, and having intermediate connections between the first location and the second location to each intermediate semiconductor region.
4. The structure of claim 1 , wherein the voltage control device is at least partly defined in at least one of: the first semiconductor region, an intermediate semiconductor region and the second semiconductor region.
5. The structure of claim 1 , wherein the first and second semiconductor region are defined in the same semiconductor layer.
6. The structure of claim 5 , wherein the semiconductor layer comprises a silicon on insulator or semiconductor on insulator layer.
7. The structure of claim 5 , wherein each non-conducting region comprises a trench isolation structure.
8. The structure of claim 7 , wherein the trench isolation structure is through a full thickness of the semiconductor layer.
9. The structure of claim 3 , wherein each conducting element comprises a resistor.
10. The structure of claim 1 , wherein each conducting element comprises a diode, or a plurality of diodes connected in series.
11. The structure of claim 10 , wherein the or each diode comprises a Zener diode.
12. A semiconductor device comprising the semiconductor structure of claim 11 , wherein the semiconductor structure is configured as: a high voltage Zener diode, or a high voltage clamp.
13. An electronic apparatus comprising the semiconductor device of claim 12 .
14. The apparatus of claim 13 , wherein the apparatus comprises an integrated circuit for discharging a mains filtering capacitor, and the semiconductor device is configured to protect the integrated circuit from overvoltage damage due to mains surge.
15. A method of fabricating the semiconductor structure of claim 1 , comprising:
providing a semiconductor layer;
defining a first and second semiconductor region of the semiconductor layer by forming a voltage isolator around a perimeter of the second semiconductor region, separating it from the first semiconductor region, the voltage isolator comprising a nested series of isolating regions, with an intermediate region of the semiconductor layer between each adjacent pair of insulating regions;
defining a voltage control device comprising a conducting element connected to at least one intermediate semiconductor region, in parallel with at least one insulating region, so as to control a voltage across the at least one insulating region.