Semiconductor wafer

1. A semiconductor wafer, comprising:

an excluded region formed on an outer periphery of the semiconductor wafer;

a plurality of semiconductor chip regions formed on an inner side of the excluded region, the plurality of semiconductor chip regions comprising different types of semiconductor chip regions;

a plurality of semiconductor chips having the same size arranged in each of the plurality of semiconductor chip regions;

a reference point chip arranged at an upper end of each of the plurality of semiconductor chip regions so as to be adjacent to the excluded region when an orientation flat side of the semiconductor wafer corresponds to an upper side of the semiconductor wafer, the reference point chip having a size the same as the size of the semiconductor chip; and

a mark chip adjacent to the reference point chip on the excluded region side of each of the plurality of semiconductor chip regions.

2. A semiconductor wafer according to claim 1 , wherein the mark chip is arranged at each side of the upper end of each of the plurality of semiconductor chip regions.

3. A semiconductor wafer according to claim 1 , wherein the mark chip comprises type distinction information and address information allowing a lot number, a wafer number, and a position on a wafer of the semiconductor chip to be distinguished.

4. A semiconductor wafer according to claim 3 , wherein the mark chip has a surface on which one of a distinguishable character and a distinguishable symbol is marked.

5. A semiconductor wafer according to claim 3 ;

wherein the mark chip comprises a plurality of fuses, and

wherein a part of the plurality of fuses is cut, to thereby write the type distinction information and the address information.