Chip select (‘CS’) multiplication in a serial peripheral interface (‘SPI’) system
View Patent ↗Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.
1. A method comprising:
monitoring, by a fall time detection circuit, a voltage of a chip select (‘CS’) signal on an CS signal line, the voltage alternating between a logic high voltage and a logic low voltage, including:
detecting a fall time of the CS signal including:
starting, responsive to the detection of a first voltage of the CS signal, an automatically incrementing counter, the counter incrementing once for each clock period of the fall time detection circuit;
stopping, responsive to a detection of a second voltage on the signal line, the automatically incrementing counter; and
calculating, in dependence upon the clock period of the fall time detection circuit and the value of the counter, a fall time for the signal line; and
if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, a CS multiplier to provide a CS signal on one of a plurality of CS outputs in dependence upon the fall time of the CS signal.
2. The method of claim 1 wherein the CS multiplier comprises the fall time detection circuit.
3. The method of claim 1 wherein detecting the fall time of the CS signal further comprises:
detecting the first voltage of the CS signal, the first voltage being less than the logic high voltage;
detecting the second voltage on the signal line, the second voltage being less than the first voltage and greater than the logic low voltage.
4. The method of claim 1 wherein:
the fall time of the signal is less than a predefined threshold responsive to an SPI master driving the signal to a logic low with an active driver; and
the fall time of the signal is not less than a predefined threshold responsive to the SPI master driving the signal to a logic low passively.
5. A fall time detection circuit configured to carry out the steps of:
monitoring, by the fall time detection circuit, a voltage of an CS signal on an CS signal line, the voltage alternating between a logic high voltage and a logic low voltage, including:
detecting a fall time of the CS signal including:
starting, responsive to the detection of a first voltage of the CS signal, an automatically incrementing counter, the counter incrementing once for each clock period of the fall time detection circuit;
stopping, responsive to a detection of a second voltage on the signal line, the automatically incrementing counter; and
calculating, in dependence upon the clock period of the fall time detection circuit and the value of the counter, a fall time for the signal line; and
if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, a CS multiplier to provide a CS signal on one of a plurality of CS outputs in dependence upon the fall time of the CS signal.
6. The fall time detection circuit of claim 5 wherein the CS multiplier comprises the fall time detection circuit.
7. The fall time detection circuit of claim 5 wherein detecting the fall time of the CS signal further comprises:
detecting the first voltage of the CS signal, the first voltage being less than the logic high voltage;
detecting the second voltage on the signal line, the second voltage being less than the first voltage and greater than the logic low voltage.
8. The fall time detection circuit of claim 5 wherein:
the fall time of the signal is less than a predefined threshold responsive to an SPI master driving the signal to a logic low with an active driver; and
the fall time of the signal is not less than a predefined threshold responsive to the SPI master driving the signal to a logic low passively.
9. A method comprising:
determining, by an SPI master, whether to configure an CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output;
if the SPI master determines to configure the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output: transmitting, by the SPI master to a fall time detection circuit and the CS multiplier, a CS signal having a fall time within a first range; and
if the SPI master determines not to configure the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output: transmitting, by the SPI master to the fall time detection circuit and the CS multiplier, a CS signal having a fall time within a second range, wherein no values are within both the first range and the second range,
wherein the fall time detection circuit is configured to: detect fall time of the CS signal and configure the CS multiplier to provide a CS signal on one of a plurality of CS outputs in dependence upon the fall time of the CS signal.
10. The method of claim 9 wherein the CS multiplier comprises the fall time detection circuit.
11. The method of claim 9 wherein:
transmitting a CS signal having a fall time within the first range further comprises driving the CS signal to a logic low with an active driver; and
transmitting a CS signal having a fall time within the second range further comprises driving the CS signal to a logic low passively.
12. An apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
determining, by an SPI master, whether to configure an CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output;
if the SPI master determines to configure the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output: transmitting, by the SPI master to a fall time detection circuit and the CS multiplier, a CS signal having a fall time within a first range; and
if the SPI master determines not to configure the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output: transmitting, by the SPI master to the fall time detection circuit and the CS multiplier, a CS signal having a fall time within a second range, wherein no values are within both the first range and the second range,
wherein the fall time detection circuit is configured to: detect fall time of the CS signal and configure the CS multiplier to provide a CS signal on one of a plurality of CS outputs in dependence upon the fall time of the CS signal.
13. The apparatus of claim 12 wherein the CS multiplier comprises the fall time detection circuit.
14. The apparatus of claim 12 wherein:
transmitting a CS signal having a fall time within the first range further comprises driving the CS signal to a logic low with an active driver; and
transmitting a CS signal having a fall time within the second range further comprises driving the CS signal to a logic low passively.
15. A computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of: determining, by an SPI master, whether to configure an CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output;
if the SPI master determines to configure the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output: transmitting, by the SPI master to a fall time detection circuit and the CS multiplier, a CS signal having a fall time within a first range; and
if the SPI master determines not to configure the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output: transmitting, by the SPI master to the fall time detection circuit and the CS multiplier, a CS signal having a fall time within a second range, wherein no values are within both the first range and the second range,
wherein the fall time detection circuit is configured to: detect fall time of the CS signal and configure the CS multiplier to provide a CS signal on one of a plurality of CS outputs in dependence upon the fall time of the CS signal.
16. The computer program product of claim 15 wherein the CS multiplier comprises the fall time detection circuit.
17. The computer program product of claim 15 wherein:
transmitting a CS signal having a fall time within the first range further comprises driving the CS signal to a logic low with an active driver; and
transmitting a CS signal having a fall time within the second range further comprises driving the CS signal to a logic low passively.
18. The computer program product of claim 15 wherein the computer readable medium comprises a storage medium.