Method and design for dynamic management of descriptors for SGL operation
View Patent ↗In an example, a method of managing direct memory access (DMA) descriptors for commands to a non-volatile semiconductor storage device includes requesting DMA descriptors from the host system for each of a plurality of the commands stored in a command random access memory (RAM). The method further includes storing the DMA descriptors for each of the plurality of the commands in free descriptor regions in a descriptor RAM. The method further includes maintaining a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions in the descriptor RAM having associated DMA descriptors.
1. A method of managing direct memory access (DMA) descriptors for a plurality of commands to a non-volatile semiconductor storage device, the method comprising:
requesting DMA descriptors from a host system for each of the plurality of commands stored in a command random access memory (RAM);
storing the DMA descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a descriptor RAM of the non-volatile semiconductor storage device; and
maintaining a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the descriptor RAM having associated DMA descriptors,
wherein at least one of the occupied descriptor regions includes multiple DMA descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.
2. The method of claim 1 , wherein each dynamic descriptor list is a linked list having a head descriptor field and a tail descriptor field, and wherein each of the plurality of commands includes pointers to the head descriptor field and the tail descriptor field, respectively, in the associated dynamic descriptor list.
3. The method of claim 1 , wherein the DMA descriptors for each of the plurality of commands include data DMA descriptors and metadata DMA descriptors.
4. The method of claim 3 , wherein each dynamic descriptor list is a linked list having a head data descriptor field, a head metadata descriptor field, and a tail descriptor field, and wherein each of the plurality of commands includes pointers to the head data descriptor field, the head metadata descriptor field, and the tail descriptor field, respectively, in the associated dynamic descriptor list.
5. The method of claim 1 , wherein each occupied descriptor region further includes at least one type flag indicating a type of the multiple DMA descriptors, at least one valid flag indicating whether the multiple DMA descriptors are valid, and at least one consumed flag indicating whether the multiple DMA descriptors have been consumed.
6. The method of claim 5 , wherein the pointer to the next occupied descriptor region in each occupied descriptor region is separately addressable in the descriptor RAM from the remaining portion of each occupied descriptor region.
7. The method of claim 1 , wherein the DMA descriptors comprise descriptors in a scatter-gather list (SGL).
8. The method of claim 1 , further comprising:
transferring associated DMA descriptors for a command to a back end of the controller; and
marking the associated DMA descriptors for the command as being consumed.
9. The method of claim 8 , further comprising:
freeing an occupied descriptor region in response to all DMA descriptors therein being marked as consumed.
10. The method of claim 8 , further comprising:
receiving an indication from the back end of the controller that the command is complete; and
freeing all occupied descriptor regions in the dynamic queue for the command.
11. A controller for a non-volatile semiconductor storage device, comprising:
a command random access memory (RAM) configured to store a plurality of commands received from a host system;
a descriptor RAM; and
a processing system having a back end configured to process active commands and a front end configured to:
fetch DMA descriptors from the host system for each of the plurality of commands stored in the command RAM;
store the DMA descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in the descriptor RAM; and
maintain a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the descriptor RAM having associated DMA descriptors,
wherein at least one of the occupied descriptor regions includes multiple DMA descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.
12. The controller of claim 11 , wherein the front end comprises a data transfer unit configured to receive the commands from the host system and to request and receive the DMA descriptors from the host system.
13. The controller of claim 11 , wherein the back end includes a DMA transfer controller configured to consume the DMA descriptors in the descriptor RAM in response to performing commands in the command RAM.
14. The controller of claim 11 , wherein each dynamic descriptor list is a linked list having a head descriptor field and a tail descriptor field, and wherein each of the plurality of commands includes pointers to the head descriptor field and the tail descriptor field, respectively, in the associated dynamic descriptor list.
15. The controller of claim 11 , wherein the DMA descriptors for each of the plurality of commands include data DMA descriptors and metadata DMA descriptors.
16. The controller of claim 15 , wherein each dynamic descriptor list is a linked list having a head data descriptor field, a head metadata descriptor field, and a tail descriptor field, and wherein each of the plurality of commands includes pointers to the head data descriptor field, the head metadata descriptor field, and the tail descriptor field, respectively, in the associated dynamic descriptor list.
17. The controller of claim 11 , wherein each occupied descriptor region further includes at least one type flag indicating a type of the multiple DMA descriptors, at least one valid flag indicating whether the multiple DMA descriptors are valid, and at least one consumed flag indicating whether the multiple DMA descriptors have been consumed.
18. The controller of claim 17 , wherein the pointer to the next occupied descriptor region in each occupied descriptor region is separately addressable in the descriptor RAM from the remaining portion of each occupied descriptor region.
19. The controller of claim 11 , wherein the DMA descriptors comprise descriptors of a scatter-gather list (SGL).
20. A non-transitory computer readable medium having stored thereon instructions that when executed by a processor cause the processor to perform a method of managing direct memory access (DMA) descriptors for a plurality of commands to a non-volatile semiconductor storage device, the method comprising:
requesting DMA descriptors from a host system for each of the plurality of commands stored in a command random access memory (RAM);
storing the DMA descriptors for each of the plurality of commands in free descriptor regions of a plurality of descriptor regions in a descriptor RAM of the non-volatile semiconductor storage device; and
maintaining a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions of the plurality of descriptor regions in the descriptor RAM having associated DMA descriptors,
wherein at least one of the occupied descriptor regions includes multiple DMA descriptors and a single pointer to a next occupied descriptor region of the plurality of descriptor regions.