METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
In a step F 2 , an isolation region and an element formation region are formed in an SOI substrate. In a step F 3 , an SOI region and a bulk region are formed. Here, an isolation insulating film of the isolation region is exposed along the entire perimeter of a sidewall of a step between the SOI region and the bulk region. In a step F 4 , a gate electrode is formed. In a step F 5 , extension implantation of a bulk transistor is carried out. Here, treatment for preventing an impurity for extension implantation from being implanted into the SOI region is performed. In a step F 6 , an elevated epitaxial layer is formed in the SOI region.
1 . A method of manufacturing a semiconductor device, comprising processes of:
preparing a substrate portion having a semiconductor layer formed on a surface of a semiconductor substrate with an insulating layer being interposed;
forming an isolation region in said substrate portion;
defining a first region and a second region adjacent to each other with respect to said substrate portion, and forming a first element formation region and a first dummy element formation region in said first region and forming a second element formation region and a second dummy element formation region in said second region by exposing said semiconductor substrate and said isolation region by allowing said semiconductor layer and said insulating layer located in said first region to remain and removing said semiconductor layer and said insulating layer located in said second region;
forming a first gate electrode and a first dummy gate electrode in said first region and forming a second gate electrode and a second dummy gate electrode in said second region;
forming a cover portion covering said first element formation region and said first dummy element formation region;
introducing an impurity of one conductivity type into said second element formation region in said second region with at least said cover portion serving as a mask after said cover portion is formed; and
forming an elevated epitaxial layer in said first element formation region with an epitaxial growth method,
in said process of forming an isolation region, said isolation region being formed such that said isolation region is exposed along an entire step formed at a boundary between said first region and said second region by removing said semiconductor layer and said insulating layer located in said second region.
2 . The method of manufacturing a semiconductor device according to claim 1 , wherein
in said process of forming a cover portion, a photoresist is formed as said cover portion so as to cover entire said first region including said first element formation region and said first dummy element formation region.
3 . The method of manufacturing a semiconductor device according to claim 1 , wherein
in said process of forming a cover portion, said first dummy gate electrode covering entire said first dummy element formation region and a photoresist covering entire said first element formation region are formed as said cover portion, and
in said process of forming an elevated epitaxial layer, said elevated epitaxial layer is formed while said entire first dummy element formation region is covered with said first dummy gate electrode.
4 . The method of manufacturing a semiconductor device according to claim 1 , having a process of forming a sidewall protection film on a sidewall of each of said first gate electrode and said first dummy gate electrode before said process of forming an elevated epitaxial layer, wherein
in said process of forming a cover portion, said first dummy gate electrode covering entire said first dummy element formation region and a photoresist covering entire said first element formation region are formed as said cover portion, and
in said process of forming an elevated epitaxial layer, said elevated epitaxial layer is formed while said entire first dummy element formation region is covered with said first dummy gate electrode and said sidewall protection film.
5 . The method of manufacturing a semiconductor device according to claim 1 , wherein
said process of forming an isolation region includes the steps of
setting as a first pattern, a pattern registered in advance as an element formation region,
setting a second pattern as a pattern corresponding to said first region,
setting as a third pattern, a portion of said first pattern located within a region of said second pattern,
setting as a fourth pattern, a pattern obtained by excluding said third pattern and a portion of said first pattern located at a boundary of said second pattern from said first pattern, and
setting as a fifth pattern, a pattern which is combination of said third pattern and said fourth pattern, and
said isolation region is formed based on said fifth pattern.
6 . The method of manufacturing a semiconductor device according to claim 1 , wherein
the process of forming a first gate electrode, a first dummy gate electrode, a second gate electrode, and a second dummy gate electrode includes steps of
setting a second pattern as a pattern corresponding to said first region,
setting as a sixth pattern, a pattern registered in advance as a gate electrode,
setting as a seventh pattern, a portion of said sixth pattern located within a region of said second region,
setting as an eighth pattern, a pattern obtained by excluding said seventh pattern and a portion of said sixth pattern located at a boundary of said second pattern from said sixth pattern, and
setting as a ninth pattern, a pattern which is combination of said seventh pattern and said eighth pattern, and
said first gate electrode, said first dummy gate electrode, said second gate electrode, and said second dummy gate electrode are formed based on said ninth pattern.
7 . The method of manufacturing a semiconductor device according to claim 2 , wherein
said process of forming a cover portion includes steps of
setting as a tenth pattern, a pattern registered in advance as a region into which an impurity is to be introduced,
setting as a second pattern, a pattern corresponding to said first region, and
setting as an eleventh pattern, a pattern obtained by excluding said second pattern from said tenth pattern, and
said photoresist covering said first region is formed based on said eleventh pattern.
8 . A semiconductor device, comprising:
a substrate portion including a semiconductor substrate and a semiconductor layer formed on said semiconductor substrate with an insulating layer being interposed;
an isolation region formed in said substrate portion;
a first region and a second region formed in said substrate portion to be adjacent to each other;
a first element formation region and a first dummy element formation region defined in said first region by said isolation region;
a second element formation region and a second dummy element formation region defined in said second region by said isolation region; and
an elevated epitaxial layer including gate electrodes formed in said first region and said second region and formed in said first element formation region,
in said first region, said first element formation region and said first dummy element formation region being formed in said semiconductor layer,
in said second region, said second element formation region and said second dummy element formation region being formed in said semiconductor substrate,
a step corresponding to a thickness of said insulating layer and said semiconductor layer being formed at a boundary between said first region and said second region, and
said isolation region being located to surround said first region along an entire perimeter of said step.
9 . The semiconductor device according to claim 8 , wherein
the impurity of one conductivity type is introduced into said second element formation region and said impurity includes nitrogen (N).
10 . The semiconductor device according to claim 8 , wherein
said gate electrode is arranged so as not to lie across said boundary between said first region and said second region.
11 . The semiconductor device according to claim 8 , wherein
said gate electrode includes
a first gate electrode formed in said first element formation region, and
a first dummy gate electrode formed in said first dummy element formation region, and
entire said first dummy element formation region is covered with said first dummy gate electrode.
12 . The semiconductor device according to claim 8 , wherein
said gate electrode includes
a first gate electrode formed in said first element formation region, and
a first dummy gate electrode formed in said first dummy element formation region,
a sidewall insulating film is formed on a sidewall of each of said first gate electrode and said first dummy gate electrode, and
entire said first dummy element formation region is covered with said first dummy gate electrode and said sidewall insulating film.