Microcomputer and method for controlling memory access
A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.
1. A microcomputer comprising:
a CPU (central processing unit);
a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU;
a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information; and
a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU,
wherein each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.
2. The microcomputer according to claim 1 ,
wherein each of the plurality of protection information storages which stores the memory protection information specifying the access permission state in the first memory protection state stores the memory protection information specifying the access prohibited state in the second memory protection state according to the reset signal.
3. The microcomputer according to claim 1 ,
wherein each of the plurality of protection information storages which stores the memory protection information specifying the access prohibited state in the first memory protection state stores the memory protection information specifying the access prohibited state in the second memory protection state according to the reset signal.
4. The microcomputer according to claim 2 ,
wherein the plurality of the protection information storages are set to a third memory protection state from the second memory protection state according to a write request output from the CPU,
the plurality of the protection information storages include at least one of the protection information storages which stores the memory protection information specifying the access permission state in the first and third memory protection states and the access prohibited state in the second memory protection state.
5. The microcomputer according to claim 2 ,
wherein the plurality of the protection information storages are set to a third memory protection state from the second memory protection state according to a write request output from the CPU,
the plurality of the protection information storages include at least one of the protection information storages which stores the memory protection information specifying the access permission state in the first memory protection state and the access prohibited state in the second and third memory protection states.
6. The microcomputer according to claim 3 ,
wherein the plurality of the protection information storages are set to a third memory protection state from the second memory protection state according to a write request output from the CPU,
the plurality of the protection information storages include at least one of the protection information storages which stores the memory protection information specifying the access prohibited state in the first and second memory protection states and the access permission state in the third memory protection state.
7. The microcomputer according to claim 3 ,
wherein the plurality of the protection information storage are set to a third memory protection state from the second memory protection state according to a write request output from the CPU,
the plurality of the protection information storages include at least one of the protection information storages which stores the memory protection information specifying the access prohibited state from the first memory protection state to the third memory protection state.
8. The microcomputer according to claim 5 ,
wherein the plurality of protection information storages further includes at least one of the protection information storages which stores the memory protection information specifying the access prohibited state from the first memory protection state to the third memory protection state.
9. The microcomputer according to claim 6 ,
wherein the plurality of protection information storages further includes at least one of the protection information storages which stores the memory protection information specifying the access prohibited state from the first memory protection state to the third memory protection state.
10. A microcomputer comprising:
a CPU (central processing unit);
a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU;
a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information; and
a reset apparatus configured to reset the plurality of protection information storages according to a request output from the CPU according to a switching of programs executed by the CPU.
11. The microcomputer according to claim 10 ,
wherein at least one of the plurality of protection information storages is set to a second memory protection state according to a reset from a first memory protection state, and wherein at least one of protection information storages which stores the memory protection information specifying the access permission state in the first memory protection state stores the memory protection information specifying the access prohibited state in the second memory protection state.
12. The microcomputer according to claim 10 , wherein each of the plurality of protection information storages which stores the memory protection information specifying the access prohibited state in the first memory protection state stores the memory protection information specifying the access prohibited state in the second memory protection state according to the reset signal.
13. The microcomputer according to claim 11 , wherein the plurality of the protection information storages are set to a third memory protection state from the second memory protection state according to a write request output from the CPU.
14. The microcomputer according to claim 13 , wherein the plurality of the protection information storages include at least one of the protection information storages which stores the memory protection information specifying the access permission state in the first and third memory protection states and the access prohibited state in the second memory protection state.
15. The microcomputer according to claim 10 , wherein the plurality of the protection information storages are set to a third memory protection state from the second memory protection state according to a write request output from the CPU.
16. The microcomputer according to claim 11 , wherein the plurality of the protection information storages include at least one of the protection information storages which stores the memory protection information specifying the access permission state in the first memory protection state and the access prohibited state in the second and third memory protection states.
17. The microcomputer according to claim 16 , wherein the plurality of protection information storages further includes at least one of the protection information storages which stores the memory protection information specifying the access prohibited state from the first memory protection state to the third memory protection state.
18. The microcomputer according to claim 10 , wherein the reset apparatus sets a plurality of the valid bit storing fields of the plurality of protection setting registers of the protection information storage to invalid state in response to the reset request signal output by the CPU.
19. A method of microcomputer comprising:
storing in a plurality of protection information storages, memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by a CPU;
determining, by a memory access control apparatus, whether or not to allow a memory access request from the CPU according to the memory protection information; and
outputting a reset signal by the reset apparatus to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU.
20. The method of microcomputer according to claim 19 , wherein each of the plurality of protection information storages which stores the memory protection information specifying the access permission state in the first memory protection state stores the memory protection information specifying the access prohibited state in the second memory protection state according to the reset signal, and
wherein each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.