MOS TRANSISTOR, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME
In a MOS transistor having a structure in which a source and a drain are raised on a substrate by using a selective epitaxial growth technique, a bulk resistance can be reduced while an impurity concentration of a silicon layer is reduced in the selective epitaxial growth. A metal oxide semiconductor transistor includes a gate having a sidewall formed on a silicon substrate, a silicon layer formed on the silicon substrate by selective epitaxial growth, and an inclination portion inclined downward in a direction opposite to the gate on at least a portion of a cross-section including the silicon layer and the gate.
1 . A semiconductor device comprising:
a semiconductor substrate having an upper surface and a plurality of active regions;
at least one of the active regions having an active upper surface which is a part of the upper surface of the semiconductor substrate;
a plurality of gates formed on the upper surface of the semiconductor substrate, a first gate being formed on a first portion of the active upper surface;
an epitaxial semiconducting layer formed on a second portion of the active upper surface, the second portion of the active upper surface not being covered by the first gate;
a plurality of dielectric spacers, each of the dielectric spacer covering a sidewall of one of the plurality of gates;
a first dielectric spacer covering a first portion of the epitaxial semiconducting layer;
a second portion of the epitaxial semiconducting layer not being covered by any one of the plurality of dielectric spacers;
the second portion of the epitaxial semiconducting layer bordering the first portion of the epitaxial semiconducting layer and an isolation region;
the isolation region surrounding the at least one of the active regions;
an upper surface of the second portion of the epitaxial semiconducting layer being etched to have a lower height than the upper surface of the first portion of the epitaxial semiconducting layer.
2 . The semiconductor device according to claim 1 , wherein the second portion of the epitaxial semiconductor layer is implanted with an impurity to form an impurity layer.
3 . The semiconductor device according to claim 2 , further comprising a sidewall interposed between one of the plurality of gates and the first dielectric spacer.
4 . The semiconductor device according to claim 3 , further comprising a first current path extending from a lower end of the sidewall toward an uppermost portion of the impurity layer, and a second current path extending from the lower end of the sidewall toward a point where the impurity layer meets the active upper surface, the first and second current paths having a same length.
5 . The semiconductor device according to claim 4 , wherein in a group of lines extending radially from the lower end of the sidewall toward the impurity layer, each line between the first and second current paths has a length that is smaller than the length of the first and second current paths.
6 . The semiconductor device according to claim 1 , wherein the second portion of the epitaxial semiconductor layer slopes downward toward the second portion of the active upper surface.
7 . The semiconductor device according to claim 1 , further comprising a sidewall interposed between one of the plurality of gates and the first dielectric spacer.
8 . The semiconductor device according to claim 7 , wherein a length of a horizontal line connecting between a lower end of the sidewall and the second portion of the epitaxial semiconductor layer is greater than or equal to a thickness of the first portion of the epitaxial semiconductor layer.
9 . The semiconductor device according to claim 7 , wherein the second portion of the epitaxial layer is inclined downward and away from the sidewall.