Semiconductor packaging identifier

1. A semiconductor package frame comprising:

a material comprising a plurality of wire openings;

a die-mounting surface area comprising a die-mounting surface; and

a plurality of identification markings included within the die-mounting surface, the plurality of identification markings to uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification markings.

2. The semiconductor package frame of claim 1 , wherein the semiconductor package frame accommodates a Quad Flat package with no lead.

3. The semiconductor package frame of claim 1 , wherein the die-mounting surface area comprises copper.

4. The semiconductor package frame of claim 1 , wherein the identification markings are dimples that extend through the die-mounting surface area at least halfway.

5. The semiconductor package frame of claim 1 , wherein the identification markings are individual binary coded markings.

6. The semiconductor package frame of claim 1 , wherein the identification markings resemble alpha numeric characters.

7. The semiconductor package frame of claim 1 , wherein the identification markings are individual dot matrix characters.

8. The semiconductor package frame of claim 1 , wherein the identification markings are visible via X-ray imagery.

9. The semiconductor package frame of claim 1 , further comprising a plurality of conductive fingers.

10. An integrated circuit package comprising:

a plurality of pins;

a plurality of wires coupled to the pins;

an integrated circuit die coupled to the plurality of wires;

a lead frame comprising:

a material comprising a plurality of wire openings;

a die-mounting surface area comprising a die-mounting surface; and

a plurality of identification markings included within the die-mounting surface, the plurality of identification markings to uniquely identify the lead frame from among other lead frames comprising different identification markings.

11. The integrated circuit package of claim 10 , wherein the lead frame accommodates a Quad Flat package with no lead.

12. The integrated circuit package of claim 10 , wherein the die-mounting surface area comprises copper.

13. The integrated circuit package of claim 10 , wherein the identification markings are dimples that extend through the die-mounting surface area at least halfway.

14. The integrated circuit package of claim 10 , wherein the identification markings are individual binary coded markings.

15. The integrated circuit package of claim 10 , wherein the identification markings resemble alpha numeric characters.

16. The integrated circuit package of claim 10 , wherein the identification markings are individual dot matrix characters.

17. The integrated circuit package of claim 10 , wherein the plurality of identification markings are visible via X-ray imagery.

18. The integrated circuit package of claim 10 , wherein the lead frame further comprises a plurality of conductive fingers disposed between the plurality of openings in the material.

19. A method for forming a lead frame comprising:

forming a plurality of wire openings in a material;

receiving identification information; and

forming a plurality of identification markings on a die-mounting surface within a die-mounting surface area of the material based on the identification information, wherein the die-mounting surface area comprises a die-mounting surface for mounting a die, the plurality of identification markings to uniquely identify the semiconductor package frame from among other semiconductor package frames comprising different identification markings.

20. The method of claim 19 , wherein the plurality of identification markings are formed via an etching process.