IP Library Granted Patent US 9,997,120
Granted Patent B2
US 9,997,120 · App. 14/680,140 · Granted Jun 12, 2018

Display device with gate floating for reducing flicker

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Quick Facts
Patent No.
US 9,997,120
App. No.
14/680,140
Granted
Jun 12, 2018
Kind
B2
Abstract

When an intermittent driving mode is carried out in a TFT using LIPS and α-Si for a pixel transistor, a flicker easily occurs. A display device includes a TFT including a gate, a source, and a drain; a signal line connected to the source; a pixel capacitance connected to the drain; a first power supply configured to supply a potential that breaks electricity conducted between the source and the drain to the gate; and a switch configured to supply a potential of the first power supply to the gate. The display device includes a scan period and a dwell period. The switch is turned on in the scan period, and the switch is turned off in the dwell period.

Claims (24)

1. A display device comprising:

a TFT including a gate, a source, and a drain;

a signal line connected to the source;

a pixel capacitance connected to the drain;

a first power supply configured to supply a potential that breaks electricity conducted between the source and the drain to the gate;

a second power supply configured to supply a potential that conducts electricity between the source and the drain to the gate;

a first switch configured to supply a potential of the first power supply to the gate;

a second switch configured to supply a potential of the second power supply to the gate; and

a third switch located between the first switch, the second switch, and the gate,

wherein:

the display device has a scan period, in which one screen is scanned, and a dwell period between the scan period and a subsequent scan period, the dwell period being the same as or longer than the scan period;

in the scan period, either one of the first switch and the second switch is turned on to supply one of the potentials of the first and second power supplies to the gate, so that the potential of the gate is fixed;

in the dwell period, the third switch is turned off so that none of the potentials of the first and second power supplies are supplied to the gate, so that the potential of the gate is floated, and

when a potential of the signal line is a positive polarity, the third switch is turned off in the dwell period, and when a potential of the signal line is a negative polarity, the first switch is turned on in the dwell period.

2. The display device according to claim 1 ,

wherein in the dwell period, a potential of the signal line is set to a predetermined potential other than 0 V at a polarity the same as a polarity of the signal line in a scan period immediately before.

3. The display device according to claim 2 ,

wherein in the dwell period, a potential of the signal line is set to an average of a picture signal potential in a scan period immediately before.

4. The display device according to claim 2 ,

wherein in the dwell period, a potential of the signal line is set to an intermediate value between a maximum value and a minimum value of a picture signal potential.

5. The display device according to claim 2 ,

wherein in the dwell period, a positive potential of the signal line is set greater than an average of a picture signal potential in a scan period immediately before, and a negative potential of the signal line is set smaller than the average of the picture signal potential in the scan period immediately before.

6. The display device according to claim 2 ,

wherein in the dwell period, a positive potential of the signal line is set to a maximum value of a picture signal potential, and a negative potential of the signal line is set to a minimum value of the picture signal potential.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2015
From: TANAKA, YUKIO; SUZUKI, DAIICHI; NAKAO, KENJI
To: JAPAN DISPLAY INC.
Reel/Frame 035344/0735 →