Phase-locked loop circuit having low close-in phase noise
View Patent ↗Phase-locked loop (PLL) circuits and methods of operation are disclosed. At frequencies that are closer to a center frequency, the phase noise characteristics contributed by a crystal oscillator in a first PLL sub-circuit dominate over the phase noise characteristics contributed by a second PLL sub-circuit, resulting in low close-in phase noise in the overall PLL circuit output signal, while at frequencies farther from the center frequency, the phase noise characteristics contributed by the second PLL sub-circuit dominate over the phase noise characteristics contributed by the crystal oscillator in the first PLL sub-circuit, resulting in low phase noise in the overall PLL circuit output signal at those frequencies.
1. A phase-locked loop (PLL) circuit for operating upon an input signal, comprising:
a crystal oscillator (XO) having an output configured to produce an XO signal distinct from the input signal;
a first PLL sub-circuit comprising a first PLL and a numerically controlled oscillator (NCO), the first PLL having a first input configured to receive the input signal and a second input configured to receive a feedback signal, the NCO having an NCO signal input coupled to an output of the first PLL and a NCO control input coupled to the output of the XO; and
a second PLL sub-circuit comprising a second PLL, the second PLL sub-circuit having a first input coupled to an output of the NCO and having a second input configured to receive the feedback signal, the second PLL sub-circuit having an output defining the feedback signal.
2. The PLL circuit of claim 1 , wherein the second PLL sub-circuit comprises a phase error detector, a loop filter, and a voltage-controlled oscillator (VCO), the loop filter having an input coupled to an output of the phase error detector, the VCO having an input coupled to an output of the loop filter, the phase error detector having a first input coupled to the output of the NCO and a second input coupled to an output of the VCO and coupled to the second input of the first PLL.
3. The PLL circuit of claim 2 , wherein the phase error detector comprises exclusive-OR logic.
4. The PLL circuit of claim 2 , wherein the VCO comprises a voltage-controlled crystal oscillator (VCXO).
5. The PLL circuit of claim 4 , wherein the VCXO has a phase noise level exceeding a phase noise level of the XO within a frequency band.
6. The PLL circuit of claim 4 , wherein the loop filter comprises a low-pass filter having a bandwidth substantially equal to a VCXO modulation bandwidth.
7. The PLL circuit of claim 1 , wherein the first PLL consists of all-digital logic.
8. The PLL circuit of claim 1 , wherein the first PLL has a bandwidth less than 1 Hz.
9. The PLL circuit of claim 1 , wherein the first PLL further comprises a frequency multiplier having an input coupled to an output of the XO and having an output coupled to the NCO control input.
10. A method for operation of a phase-locked loop (PLL) circuit, the PLL circuit comprising a crystal oscillator (XO), a first PLL sub-circuit, and a second PLL sub-circuit, the first PLL sub-circuit comprising a first PLL and a numerically controlled oscillator (NCO), the first PLL having a first input configured to receive an input signal and a second input configured to receive a feedback signal, the NCO having an NCO signal input coupled to an output of the first PLL and a control input coupled to an output of the crystal oscillator, the second PLL sub-circuit comprising a second PLL, the second PLL sub-circuit comprising a phase error detector, a low-pass filter, and a voltage-controlled crystal oscillator (VCXO), the low-pass filter having an input coupled to an output of the phase error detector, the VCXO having an input coupled to an output of the low-pass filter, the phase error detector having a first input coupled to the output of the NCO and a second input coupled to an output of the VCXO, the method comprising:
the first PLL sub-circuit receiving an input signal and locking the input signal to a frequency of the XO; and
the second PLL sub-circuit providing an output signal having a first phase noise characteristic corresponding to a phase noise characteristic of the XO at frequencies below a cutoff frequency of the low-pass filter, and providing the output signal with a second phase noise characteristic corresponding to a phase noise characteristic of the VCXO at frequencies above the cutoff frequency of the low-pass filter.
11. The method of claim 10 , wherein the second PLL sub-circuit generating an output signal comprises the phase error detector performing an exclusive-OR logic operation.
12. The method of claim 10 , wherein the VCXO has a phase noise level exceeding a phase noise level of the XO within a frequency band.
13. The method of claim 12 , wherein the low-pass filter has a bandwidth substantially equal to a VCXO modulation bandwidth.
14. The method of claim 10 , wherein the first PLL consists of all-digital logic.
15. The method of claim 10 , wherein the first PLL has a bandwidth less than 1 Hz.
16. The method of claim 10 , wherein the first PLL sub-circuit further multiplies a frequency of an XO signal and provides a multiplied signal to the NCO control input.
17. The PLL circuit of claim 4 , wherein:
the loop filter comprises a low-pass filter;
the second PLL sub-circuit is configured to generate an output signal having a first phase noise characteristic corresponding to a phase noise characteristic of the XO at frequencies below a cutoff frequency of the low-pass filter, and providing the output signal with a second phase noise characteristic corresponding to a phase noise characteristic of the VCXO at frequencies above the cutoff frequency of the low-pass filter.