Circuits for phase-cut analog dimming of solid state light sources

1. A circuit comprising:

an anchoring circuit in communication with a dimming controller circuit, the anchoring circuit comprising a proportional direct current (DC) voltage input, a biasing voltage input, a connection to a ground reference, and an output in communication with the dimming controller circuit;

wherein the anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages, and wherein the anchoring circuit comprises:

a first resistor comprising a first lead coupled to a positive proportional DC voltage and comprising a second lead;

a second resistor comprising a first lead coupled to a biasing voltage and comprising a second lead;

a third resistor comprising a first lead coupled to the biasing voltage and comprising a second lead;

a fourth resistor comprising a first lead coupled to the second lead of the second resistor and comprising a second lead;

a fifth resistor comprising a first lead coupled to a second lead of the third resistor and comprising a second lead;

a first transistor comprising a first lead coupled to the second lead of the second resistor, a second lead coupled to the second lead of the first resistor, and a third lead coupled to the ground reference;

a second transistor comprising a first lead coupled to the second lead of the fourth resistor, a second lead coupled to the second lead of the third resistor, and a third lead coupled to the ground reference; and

a third transistor comprising a first lead coupled to the second lead of the fifth resistor, a second lead comprising an output of the anchoring circuit, and a third lead coupled to the ground reference.

2. The circuit of claim 1 , wherein the first transistor comprises a silicon controlled rectifier (SCR) and wherein the first lead of the SCR comprises an anode, the second lead comprises a gate, and the third lead comprises a cathode.

3. The circuit of claim 1 , wherein the second transistor comprises an NPN transistor and wherein the first lead of the NPN transistor comprises a base of the NPN transistor, the second lead comprises an emitter of the NPN transistor, and the third lead comprises a collector of the NPN transistor.

4. The circuit of claim 1 , wherein the third transistor comprises a MOSFET and wherein the first lead of the MOSFET comprises a gate of the MOSFET, the second lead comprises a drain of the MOSFET, and the third lead comprises a source of the MOSFET.

5. The circuit of claim 1 , wherein for a first input voltage the third transistor is open, the second transistor is closed, and the first transistor is open.

6. The circuit of claim 1 , wherein for a second input voltage the third transistor is closed, the second transistor is open, and the first transistor is closed.

7. A phase cut dimming circuit comprising:

a dimming controller circuit, the dimming controller circuit comprising an input receiving a line voltage, a connection to a ground, and an output;

an anchoring circuit in communication with the dimming controller circuit, the anchoring circuit comprising an input, a connection to a ground, and an output in communication with the dimming controller circuit;

wherein the anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages, and wherein the anchoring circuit comprises:

a first resistor comprising a first lead coupled to a positive proportional DC voltage and comprising a second lead;

a second resistor comprising a first lead coupled to a biasing voltage and comprising a second lead;

a third resistor comprising a first lead coupled to the biasing voltage and comprising a second lead;

a fourth resistor comprising a first lead coupled to the second lead of the second resistor and comprising a second lead;

a fifth resistor comprising a first lead coupled to a second lead of the third resistor and comprising a second lead;

a first transistor comprising a first lead coupled to the second lead of the second resistor, a second lead coupled to the second lead of the first resistor, and a third lead coupled to the ground reference;

a second transistor comprising a first lead coupled to the second lead of the fourth resistor, a second lead coupled to the second lead of the third resistor, and a third lead coupled to the ground reference; and

a third transistor comprising a first lead coupled to the second lead of the fifth resistor, a second lead comprising an output of the anchoring circuit, and a third lead coupled to the ground reference.

8. The phase cut dimming circuit of claim 7 , wherein the dimming controller circuit comprises:

a controller comprising an input coupled to a center point of a voltage divider circuit, the controller providing an output to couple to a primary side regulated analog flyback converter; and

wherein the voltage divider circuit is coupled between the line voltage and the ground, and wherein the voltage divider circuit comprises:

a first resistor comprising a first lead coupled to the input of the controller and a second lead coupled to the ground;

a second resistor comprising a first lead coupled to the input of the controller and a second lead coupled to the line voltage, and wherein the first lead of the second resistor and the first lead of the first resistor comprise the center point of the voltage divider circuit; and

a third resistor comprising a first lead coupled to the center point of the voltage divider circuit and a second lead to couple to an input of the anchoring circuit.

9. The phase cut dimming circuit of claim 7 , wherein the first transistor comprises a silicon controlled rectifier (SCR) and wherein the first lead of the SCR comprises an anode, the second lead comprises a gate, and the third lead comprises a cathode.

10. The phase cut dimming circuit of claim 7 , wherein the second transistor comprises an NPN transistor and wherein the first lead of the NPN transistor comprises a base of the NPN transistor, the second lead comprises an emitter of the NPN transistor, and the third lead comprises a collector of the NPN transistor.

11. The phase cut dimming circuit of claim 7 , wherein the third transistor comprises a MOSFET and wherein the first lead of the MOSFET comprises a gate of the MOSFET, the second lead comprises a drain of the MOSFET, and the third lead comprises a source of the MOSFET.

12. The phase cut dimming circuit of claim 7 , wherein for a first input voltage, the third transistor is open, the second transistor is closed, and the first transistor is open.

13. The phase cut dimming circuit of claim 7 , wherein for a second input voltage, the third transistor is closed, the second transistor is open, and the first transistor is closed.

14. A phase cut dimming circuit comprising:

a dimming controller circuit, the dimming controller circuit comprising an input receiving a line voltage, a connection to a ground, and an output;

an anchoring circuit in communication with the dimming controller circuit, the anchoring circuit comprising an input, a connection to a ground, and an output in communication with the dimming controller circuit;

wherein the anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages; and

wherein the dimming controller circuit comprises:

a controller comprising an input coupled to a center point of a voltage divider circuit, the controller providing an output to couple to a primary side regulated analog flyback converter; and

wherein the voltage divider circuit is coupled between the line voltage and the ground, and wherein the voltage divider circuit comprises:

a first resistor comprising a first lead coupled to the input of the controller and a second lead coupled to the ground;

a second resistor comprising a first lead coupled to the input of the controller and a second lead coupled to the line voltage, and wherein the first lead of the second resistor and the first lead of the first resistor comprise the center point of the voltage divider circuit; and

a third resistor comprising a first lead coupled to the center point of the voltage divider circuit and a second lead to couple to an input of the anchoring circuit.