IP Library Granted Patent US 9,740,548
Granted Patent B2
US 9,740,548 · App. 14/682,621 · Granted Aug 22, 2017

Error source identification on time-of-day network

Inventor: Manish Kumar Chowdhary (Bangalore, IN)
Assignee: International Business Machines Corporation
G06F11/0757G06F11/079G06F11/0724G06F11/0772H04L43/0864
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Quick Facts
Patent No.
US 9,740,548
App. No.
14/682,621
Granted
Aug 22, 2017
Kind
B2
Abstract

In an approach to identifying a source of a time-of-day network error, one or more computers increment a first counter and a second counter on each of one or more computer processors simultaneously. The one or more computers determine whether an error is detected in the one or more computer processors. In response to determining the error is detected, the one or more computers freeze the second counter on the one or more computer processors associated with the detected error. The one or more computers determine on which of the one or more computer processors the second counter is frozen. The one or more computers report a time-of-day network error, where reporting a time-of-day network error includes assigning a priority to one or more sources of the time-of-day network error.

Claims (20)

1. A computer system for identifying a source of a time-of-day network error, the computer system comprising:

one or more computer processors;

one or more computer readable storage media;

program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors; and

wherein the system is operable to:

increment a first counter and a second counter on each of the one or more computer processors simultaneously;

determine whether an error is detected in the one or more computer processors;

responsive to determining the error is detected, freeze the second counter on the one or more computer processors associated with the detected error, and notify a service processor of the error via a system interrupt, wherein the service processor is one of the one or more computer processors;

determine on which of the one or more computer processors the second counter is frozen; and

report a time-of-day network error, wherein reporting a time-of-day network error includes assigning a priority to one or more sources of the time-of-day network error.

2. The computer system of claim 1 , wherein the system being operable to report the time-of-day network error further comprises, responsive to determining on which of the one or more computer processors the second counter is frozen, the system being operable to determine that only a first computer processor of the one or more computer processors includes a frozen second counter.

3. The computer system of claim 2 , wherein the assigned priority of the one or more sources of the time-of-day network error is a) the first computer processor, and b) a bus between the first computer processor and a second computer processor, wherein the first computer processor is a lowest computer processor in a time-of-day signal propagation hierarchy.

4. The computer system of claim 1 , wherein the system being operable to report the time-of-day network error further comprises:

responsive to determining on which of the one or more computer processors the second counter is frozen, the system being operable to determine whether more than one of the one or more computer processors includes a frozen second counter, wherein each frozen second counter value of the more than one of the one or more computer processors is the same; and

responsive to determining that more than one computer processor of the one or more computer processors includes a frozen second counter, the system being operable to determine that each of the one or more computer processors in the time-of-day network includes a frozen second counter, wherein one of the one or more computer processors is a master processor.

5. The computer system of claim 4 , wherein the assigned priority of the one or more sources of the time-of-day network error is a) an oscillator, b) the master processor, and c) a path between the oscillator and the master processor, wherein the oscillator feeds one or more signals to the master processor.

6. The computer system of claim 4 , wherein the system being operable to report the time-of-day network error further comprises, the system being operable to determine that each of the one or more computer processors in the time-of-day network does not include a frozen second counter, wherein each frozen second counter value is the same.

7. The computer system of claim 6 , wherein the assigned priority of the one or more sources of the time-of-day network error is a) a bus that communicates to a slave processor that is topmost in the time-of-day signal propagation hierarchy of the one or more processors that include a frozen second counter, and b) the slave processor that is topmost in the time-of-day signal propagation hierarchy of the one or more processors that include a frozen second counter.

8. The computer system of claim 6 , wherein the one or more computer processors that include a frozen second counter share a branch of a time-of-day signal propagation hierarchy.

9. The computer system of claim 1 , wherein the error is a time-of-day signal propagation error.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2015
From: CHOWDHARY, MANISH KUMAR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035389/0955 →
Continuity (1)
Related Publication 20160299802A1 · Oct 13, 2016