Error detection and rejection for a diagnostic testing system
View Patent ↗A system for measuring a property of a sample is provided. The system comprises a diagnostic measuring device having a memory and a diagnostic test strip for collecting the sample. The strip has embedded thereon a pattern representative of at least first data and second data, the first data being data representing at least one of parameters related to measuring the property, codes usable for calibration of the diagnostic measuring device, or parameters indicating proper connection between the measuring device and the test strip and the second data usable for detecting and rejecting potential errors affecting the proper measurement of the property.
1. A system for measuring a property of a sample fluid, comprising:
a diagnostic measuring device having a connector configured to receive a test strip for collecting the sample fluid, the strip having information including a first code embedded thereon, the first code comprising a plurality of bits arranged in a physical arrangement; and
the diagnostic device further comprising a controller programmed to perform an error detection routine comprising:
reading the plurality of bits of the first code;
determining a probability of each bit to cause a read error in the first code;
constructing a logical arrangement of the bits different than the physical arrangement based on the probability, wherein the logical arrangement results in a logically arranged code comprising the bits arranged such that the impact of potential read errors is minimized;
performing an error detection and rejection algorithm on the logically arranged code; and
determining the constituent level of the sample fluid if the error detection and rejection algorithm detects an acceptable error or does not detect an error in the logically arranged code.
2. The system according to claim 1 , wherein the logical arrangement comprises the bits arranged such that the hit having the highest probability of causing a read error is logically replaced by the bit having the lowest probability of causing a read error, and the bit having the lowest probability of causing a read error is logically replaced by the bit having the highest probability of causing a read error.
3. The system according to claim 2 , wherein the logical arrangement results in the logically arranged code which is read in sequence.
4. The system according to claim 2 , wherein the logical arrangement results in the logically arranged code which is not read in sequence.