Methods and Apparatus for Deuterium Anneal of Multi-Layered Semiconductor Structure
Methods and apparatus for passivation of semiconductor interfaces by deuterium annealing are described. Harmonic improvements after deuterium annealing of a SOI semiconductor device with a trap-rich layer was demonstrated. Secondary ion mass spectroscopy after deuterium anneal shows a deuterium rich interface layer at the BOX-trap-rich layer interface of a MOSFET semiconductor device.
1 . A semiconductor device comprising:
a trap-rich region;
a buried oxide layer on the trap-rich region;
a semiconductor layer on the buried oxide layer; and
a deuterium rich region at an interface between the buried oxide layer and the trap-rich region.
2 . The device of claim 1 , wherein the trap-rich region comprises polycrystalline silicon.
3 . The device of claim 1 , wherein the buried oxide comprises silicon dioxide.
4 . The device of claim 1 further comprising a substrate layer under the buried oxide layer and wherein the trap-rich region comprises a region of the substrate layer having a more heavily disrupted crystal structure than other parts of the substrate layer.
5 . The device of claim 4 , wherein the substrate layer comprises silicon.
6 . The device of claim 5 , wherein the substrate layer comprises a silicon ( 100 ) plane.
7 . The device of claim 4 , wherein the trap-rich region spans only a portion of a width of the substrate layer.
8 . The device of claim 1 , wherein the deuterium rich region is within 2 μm above and below the interface.
9 . The device of claim 8 , wherein the deuterium rich region is within 0.2 μm above and below the interface.
10 . The device of claim 1 , wherein the deuterium rich interface layer has a half peak width of less than 1 micron by secondary ion mass spectroscopy.
11 . The device of claim 10 , wherein the half peak width is less than 0.1 micron by secondary ion mass spectroscopy.
12 . The device of claim 1 , wherein the deuterium rich interface layer comprises more deuterium than hydrogen.
13 . The device of claim 1 , further comprising a transistor over the buried oxide layer.
14 . The device of claim 1 , further comprising a coplanar waveguide over the buried oxide layer.
15 . The device of claim 1 , wherein the trap-rich region comprises at least one of polycrystalline silicon carbide and amorphous silicon carbide.
16 . A method of deuterium annealing a semiconductor device comprising:
providing a semiconductor device wafer comprising:
a trap-rich region;
a buried oxide layer on the trap-rich region;
a semiconductor layer on the buried oxide layer; and
an interface between the buried oxide layer and the trap-rich region; and
contacting the semiconductor device wafer with deuterium gas at a temperature of at least 20° C. and a pressure of at least 1 atmosphere for an interval of time.
17 . The method of claim 16 , wherein the temperature is in a range between 200° C. to 500° C.
18 . The method of claim 17 , wherein the temperature is in a range between 300° C. to 450° C.
19 . The method of claim 18 , wherein the temperature is 400° C.
20 . The method of claim 16 , wherein the pressure is in a range between 5 atmospheres to 30 atmospheres.
21 . The method of claim 20 , wherein the pressure is 20 atmospheres.
22 . The method of claim 16 , wherein the interval of time is at least 5 minutes.
23 . The method of claim 22 , wherein the interval of time is at least 30 minutes.
24 . The method of claim 23 , wherein the interval of time is at least 60 minutes.
25 . The method of claim 16 , wherein the semiconductor device wafer further comprises a hydrogen anneal at the interface.
26 . The method of claim 25 , wherein a region at the interface comprises more deuterium than hydrogen.
27 . The method of claim 16 , wherein the trap-rich region comprises at least one of polycrystalline silicon carbide and amorphous silicon carbide.