Reduction of read disturb errors

1. A memory device comprising:

a plurality of memory cells configured to store data received from a source external to the memory device; and

at least one modified memory cell associated with the plurality of memory cells that is configured in such a manner that it is more susceptible to a read disturb error than the plurality of memory cells, each of the plurality of memory cells and the modified memory cell including a floating gate transistor; and

circuitry for applying a voltage to a gate of the modified memory cell when a voltage is applied to a gate of at least one of the plurality of memory cells, wherein voltages are applied to the gates of the plurality of memory cells and the modified memory cell during a Read operation, the voltages that are applied to the gates of the plurality of memory cells varying depending on whether the memory cell is being read during the Read operation;

wherein an amount of time the voltage is applied to the gate of the modified memory cell during a Read operation is greater than an amount of time a voltage is applied to the gate of one of the plurality of memory cells that is not being read as part of the Read operation, such that the greater amount of time over which the voltage is applied to the gate of the modified cell configures the modified memory cell so that it is more susceptible to a read disturb error than the plurality of memory cells.

2. The memory device of claim 1 wherein the voltage applied to the gate of the modified memory cell during a Read operation is greater than the voltage applied to the gate of one of the plurality of memory cells that is not being read as part of the Read operation, wherein the greater gate voltage configures the modified memory cell such that it is more susceptible to a read disturb error than the plurality of memory cells.

3. The memory device of claim 1 wherein the modified memory cell is constructed in a manner that is different from the plurality of memory cells and such construction configures the modified memory cell in such a manner that it is more susceptible to a read disturb error than the plurality of memory cells.

4. The memory device of claim 3 wherein the modified memory cell is constructed such that the size of its floating gate transistor is different from the size of the floating gate transistors for the plurality of memory cells.

5. The memory device of claim 1 wherein the construction of the modified memory cell is substantially the same as the plurality of memory cells and further including circuitry to apply voltages to the modified memory cell to configure the modified memory cell such that, as a result of the applied voltages, it is more susceptible to read disturb errors than the plurality of memory cells.

6. The memory device of claim 1 further including circuitry for detecting a read disturb error in the modified memory cell and for moving the data stored within the plurality of memory cells to new physical locations upon the detection of the read disturb error.

7. Apparatus for inhibiting errors in a group of memory cells in a memory device, the apparatus comprising:

at least one detecting cell comprising a floating gate transistor that is associated with the group of memory cells;

circuitry for applying a voltage to a gate of the detecting cell each time one of the memory cells within the group of memory cells is accessed as part of a Read operation;

a sensor coupled to the detecting cell and adapted to sense an electrical characteristic associated with the detecting cell that corresponds to the amount of charge stored on the floating gate transistor of the detecting cell; and

a comparator coupled to the sensor and adapted to compare the sensed electrical characteristic to a reference signal and provide an output, the output of the comparator generally providing an indication of increased likelihood of an error occurring within the group of memory cells;

wherein an amount of time the voltage is applied to the gate of the detecting cell during a Read operation is greater than an amount of time a voltage is applied to one of the memory cells within the group of memory cells that is not being read as part of the Read operation, such that the greater amount of time over which the voltage is applied to the gate of the detecting cell configures the detecting cell so that it is more susceptible to a read disturb error than the group of memory cells.

8. The apparatus of claim 7 wherein the group of memory cells and the detecting cell are all located within the same bitline.

9. The apparatus of claim 7 wherein the group of memory cells constitutes a Block of memory cells.

10. The apparatus of claim 9 further including a second detecting cell associated with the Block of memory cells.

11. The apparatus of claim 7 wherein the construction of the detecting cell is the same as the construction of each of the memory cells within the group of memory cells.

12. The apparatus of claim 7 wherein the sensed electrical characteristic is voltage and wherein the reference signal is a reference voltage.

13. The apparatus of claim 12 further comprising circuitry coupled to the comparator for moving the data stored in the group of memory cells to new physical locations when the output of the comparator indicates that the sensed voltage exceeds the reference voltage.

14. The apparatus of claim 7 wherein the circuitry for moving the data stored in the group of memory cells moves all of the data in the group of memory cells to new physical locations when the output of the comparator indicates that there is an increased likelihood of an error.

15. A method of reducing read disturb errors in a memory device composed of a memory space formed from a plurality of memory cells, the memory space containing physical address locations to which data may be stored, the physical address locations being grouped into Pages and at least one Block, where each Page comprises a plurality of physical address locations that are addressed at the same time and each Block comprises a collection of physical address locations that may be erased through a single erase operation, the method comprising:

receiving a Read request directed to a given Page within a Block;

providing a voltage to: (i) the memory cells in the Pages within the Block that are not the target of the Read request, and (ii) at least one modified memory cell associated with the Block; and

providing an output signal indicative of possible errors within the memory cells within the Block;

wherein an amount of time the voltage is applied to the at least one modified memory cell during a Read operation is greater than an amount of time a voltage is applied to the memory cells in the Pages within the Block that are not the target of the Read request, such that the greater amount of time over which the voltage is applied to the at least one modified memory cell configures the at least one modified memory cell so that it is more susceptible to a read disturb error than the memory cells in the Pages within the Block that are not the target of the Read request.

16. The method of claim 15 wherein the memory space includes address locations grouped into a plurality of Blocks, further comprising receiving the output signal and moving the data stored within the Pages of the Block to pages within a different Block.

17. The method of claim 16 wherein the moving the data for each Page within the Block is performed upon the receipt of a Read request directed to the Page.

18. The method of claim 15 further comprising initializing the output signal of the to a predetermined level upon the performance of an erase operation on the Block.