Fabrication method and structure of semiconductor non-volatile memory device
A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
1. A manufacturing method of a semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising the steps of:
(a) forming a first insulating film over the semiconductor substrate of the memory cell region and the peripheral circuit region;
(b) forming a first conductive film over the first insulating film of the memory cell region and the peripheral circuit region;
(c) selectively patterning the first conductive film of the memory cell region while leaving the first conductive film of the peripheral circuit region, thereby forming a first gate electrode in the memory cell region;
(d) forming a second insulating film including a charge storing region over the memory cell region and the peripheral circuit region after the step (c);
(e) forming a second conductive film over the second insulating film of the memory cell region and the peripheral circuit region;
(f) etching back the second conductive film, thereby removing the second conductive film in the peripheral circuit region and forming a second gate electrode via the second insulating film on a sidewall of the first gate electrode in the memory cell region; and
(g) patterning the first conductive film of the peripheral circuit region, thereby forming a third gate electrode in the peripheral circuit region after the step (f).
2. The manufacturing method of a semiconductor device according to claim 1 ,
wherein, in the step (f), spacer gates comprised of the second conductive film are formed on both sidewalls of the first gate electrode, and
the manufacturing method further comprises a step of removing the spacer gate formed on one sidewall of the first gate electrode before the step (g).
3. The manufacturing method of a semiconductor device according to claim 1 ,
wherein, by doping an impurity with using the first gate electrode, the second gate electrode and the third gate electrode as masks after the step (g), first impurity diffusion layers configured to function as a source and a drain of a memory cell formed in the memory cell region are formed in the semiconductor substrate of the memory cell region, and second impurity diffusion layers configured to function as a source and a drain of a MISFET formed in the peripheral circuit region are formed in the semiconductor substrate of the peripheral circuit region.
4. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the manufacturing method further comprises: a step of forming a first well by implanting an impurity of a first conductivity type into the semiconductor substrate of the memory cell region before the step (a);
a step of forming a first channel region by implanting an impurity of the first conductivity type into the first well before the step (a); and
a step of forming a second channel region by implanting an impurity of a second conductivity type opposite to the first conductivity type into the first well after the step (c) and before the step (d).
5. The manufacturing method of a semiconductor device according to claim 4 ,
wherein a charge density of the impurity of the first channel region is formed so as to be higher than a charge density of the impurity of the second channel region.
6. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the charge storing region includes a silicon nitride film.
7. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the second insulating film is comprised of a first silicon oxide film formed over the semiconductor substrate, a silicon nitride film formed over the first silicon oxide film and a second silicon oxide film formed over the silicon nitride film.
8. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the peripheral circuit region includes a first region and a second region,
the manufacturing method further comprises, before the step (a), the steps of:
(a1) forming a third insulating film over the semiconductor substrate of the memory cell region and the peripheral circuit region; and
(a2) removing the third insulating film of the memory cell region and the first region of the peripheral circuit region, while leaving the third insulating film of the second region of the peripheral circuit region after the step (a1),
in the step (a), the first insulating film is formed over the semiconductor substrate of the memory cell region and the first and second regions of the peripheral circuit region, and
in the step (g), the first conductive film of the peripheral circuit region is patterned, thereby forming the third gate electrode in the first region of the peripheral circuit region and forming a fourth gate electrode in the second region of the peripheral circuit region.
9. A manufacturing method of a semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising the steps of:
(a) forming a first insulating film over the semiconductor substrate of the memory cell region and the peripheral circuit region;
(b) forming a first conductive film over the first insulating film of the memory cell region and the peripheral circuit region;
(c) selectively patterning the first conductive film of the memory cell region while leaving the first conductive film of the peripheral circuit region, thereby forming a first gate electrode in the memory cell region;
(d) forming a second insulating film having a charge storing region over the memory cell region and the peripheral circuit region after the step (c);
(e) forming a second conductive film over the second insulating film of the memory cell region and the peripheral circuit region;
(f) etching back the second conductive film, thereby removing the second conductive film in the peripheral circuit region and forming a second gate electrode via the second insulating film on a sidewall of the first gate electrode in the memory cell region; and
(g) patterning the first conductive film of the peripheral circuit region, thereby forming a conductive film pattern in a region where a gate electrode of the peripheral circuit region is to be formed, after the step (f).
10. The manufacturing method of a semiconductor device according to claim 9 ,
wherein, in the step (f), spacer gates comprised of the second conductive film are formed on both sidewalls of the first gate electrode, and
the manufacturing method further comprises a step of removing the spacer gate formed on one sidewall of the first gate electrode before the step (g).
11. The manufacturing method of a semiconductor device according to claim 9 ,
wherein, by doping an impurity with using the first gate electrode, the second gate electrode and the conductive film pattern as masks after the step (g), first impurity diffusion layers configured to function as a source and a drain of a memory cell formed in the memory cell region are formed in the semiconductor substrate of the memory cell region, and second impurity diffusion layers configured to function as a source and a drain of a MISFET formed in the peripheral circuit region are formed in the semiconductor substrate of the peripheral circuit region.
12. The manufacturing method of a semiconductor device according to claim 9 ,
wherein the manufacturing method further comprises: a step of forming a first well by implanting an impurity of a first conductivity type into the semiconductor substrate of the memory cell region before the step (a);
a step of forming a first channel region by implanting an impurity of the first conductivity type into the first well before the step (a); and
a step of forming a second channel region by implanting an impurity of a second conductivity type opposite to the first conductivity type into the first well after the step (c) and before the step (d).
13. The manufacturing method of a semiconductor device according to claim 12 ,
wherein a charge density of the impurity of the first channel region is formed so as to be higher than a charge density of the impurity of the second channel region.
14. The manufacturing method of a semiconductor device according to claim 9 ,
wherein the charge storing region includes a silicon nitride film.
15. The manufacturing method of a semiconductor device according to claim 9 ,
wherein the second insulating film is comprised of a first silicon oxide film formed over the semiconductor substrate, a silicon nitride film formed over the first silicon oxide film and a second silicon oxide film formed over the silicon nitride film.
16. The manufacturing method of a semiconductor device according to claim 9 ,
wherein the peripheral circuit region includes a first region and a second region,
the manufacturing method further comprises, before the step (a), the steps of:
(a1) forming a third insulating film over the semiconductor substrate of the memory cell region and the peripheral circuit region; and
(a2) removing the third insulating film of the memory cell region and the first region of the peripheral circuit region, while leaving the third insulating film of the second region of the peripheral circuit region after the step (a1),
in the step (a), the first insulating film is formed over the semiconductor substrate of the memory cell region and the first and second regions of the peripheral circuit region, and
in the step (g), the first conductive film of the peripheral circuit region is patterned, thereby forming the conductive film pattern in each of the first region and the second region of the peripheral circuit region.