THROUGHPUT SCALING IN A RECEIVER
A receiver comprises a plurality of sequence estimation circuits. The receiver receives a signal that comprises a plurality of frames. For each one of the frames, the receiver samples the received signal resulting in a first plurality of samples corresponding to a preamble of the one of the frames and a second plurality of samples corresponding to a plurality of symbols of the one of the frames. A value of each sample of the second plurality of samples depends on several of the symbols of the one of the frames. The receiver splits the signal at preambles of the frames and demultiplexes the frames to generate a plurality of signals. The receiver may process the signals in parallel. The processing may comprise resetting of a state of each of the plurality of sequence estimation circuits upon detection of each preamble in a respective one of the plurality of signals.
1 . A method comprising:
in a receiver comprising a plurality of sequence estimation circuits:
receiving a signal that comprises a plurality of frames;
splitting said signal at preambles of said plurality of frames and demultiplexing said plurality of frames to generate a plurality of signals; and
processing said plurality of signals in parallel via said plurality of sequence estimation circuits, wherein said processing comprises:
resetting a state of each of said plurality of sequence estimation circuits upon detecting each preamble in a respective one of said plurality of signals;
generating a model of nonlinearity experienced by said received signal en route to said receiver;
distorting symbol candidates using said model of nonlinearity; and
calculating an error based on said distorted symbol candidates and said received signal.
2 . The method of claim 1 , comprising:
for each one of said frames, sampling said received signal to generate a plurality of samples corresponding to a plurality of symbols of said one of said frames, wherein a value of each sample of said plurality of samples depends on more than one of said symbols of said one of said frames.
3 . The method of claim 1 , comprising:
receiving said signal via a channel that introduces additive white Gaussian noise and nonlinear distortion, the combined effects of which result in a signal to noise and distortion power ratio (SINAD) of said received signal that is less than or equal to said receiver's threshold signal to noise power ratio (SNR) plus 6 dB.
4 . The method of claim 1 , comprising performing, by each of said plurality of sequence estimation circuits, reduced state sequence estimation.
5 . The method of claim 4 , comprising reproducing, by said plurality of sequence estimation circuits, a nonlinearity experienced by said received signal en route to said receiver.
6 . The method of claim 5 , comprising dynamically adapting said circuitry for reproducing said nonlinearity based on contents of said received signal.
7 . The method of claim 1 , comprising generating soft bit decisions from symbol decisions and symbol hypotheses generated by said plurality of sequence estimation circuits.
8 . The method of claim 1 , comprising outputting, by plurality of sequence estimation circuits, symbol decisions for said plurality of frames of said received signal at a rate is less than a rate at which symbols of said frames of said received signal arrive at said receiver.
9 . The method of claim 1 , comprising outputting, by said plurality of sequence estimation circuits, bit log-likelihood ratios for said received signal at a rate that is less than a rate at which bits of said received signal arrive at said receiver.
10 . The method of claim 1 , comprising adding, during said splitting, one or more fixed-value padding symbols to each of said plurality of frames.
11 . The method of claim 1 , wherein resetting said state in response to a particular preamble of a particular one of said plurality of frames comprises:
determining a phase of said particular preamble; and
using said phase of said particular preamble as an initial phase for processing symbols of said particular frame.
12 . The method of claim 1 , comprising, in each of said sequence estimation circuits, equalizing a respective one of said plurality of signals.
13 . The method of claim 1 , comprising equalizing said received signal prior to said splitting said received signal.
14 . The method of claim 1 , comprising, in each of said sequence estimation circuits, correcting a phase error of a respective one of said plurality of signals.
15 . The method of claim 1 , comprising correcting a phase of said received signal prior to said splitting of said received signal.
16 . A system comprising:
a receiver that comprises a digital front-end circuit and a plurality of sequence estimation circuits, wherein:
said digital front-end circuit is operable to:
receive a signal that comprises a plurality of frames;
split said signal at preambles of said plurality of frames and demultiplex said plurality of frames to generate a plurality of signals; and
said plurality of sequence estimation circuits are operable to:
process said plurality of signals in parallel, wherein said processing of said plurality of signals comprises a resetting of a state of each of said plurality of sequence estimation circuits upon detection of each preamble in a respective one of said plurality of signals;
generate a model of nonlinearity experienced by said received signal en route to said receiver;
distort symbol candidates using said model of nonlinearity; and
calculate an error based on said distorted symbol candidates and said received signal.
17 . The system of claim 16 , wherein said receiver is operable to:
for each one of said frames, sample said received signal to generate a plurality of samples corresponding to a plurality of symbols of said one of said frames, wherein a value of each sample of said plurality of samples depends on more than one of said symbols of said one of said frames.
18 . The system of claim 16 , comprising:
receiving said signal via a channel that introduces additive white Gaussian noise and nonlinear distortion, the combined effects of which result in a signal to noise and distortion power ratio (SINAD) of said received signal that is less than or equal to said receiver's threshold signal to noise power ratio (SNR) plus 6 dB.
19 . The system of claim 16 , wherein each of said sequence estimation circuits is operable to perform reduced state sequence estimation.
20 . The system of claim 19 , wherein said sequence estimation circuits comprise circuitry operable to reproduce a nonlinearity experienced by said received signal en route to said receiver.
21 . The system of claim 20 , wherein said circuitry for reproducing said nonlinearity is adapted dynamically based on contents of said received signal.
22 . The system of claim 16 , wherein said receiver is operable to generate soft bit decisions from symbol decisions generated by said plurality of sequence estimation circuits.
23 . The system of claim 16 , wherein a rate at which each of said plurality of sequence estimation circuits is operable to output symbol decisions for said plurality of frames of said received signal is less than a rate at which symbols of said frames of said received signal arrive at said receiver.
24 . The system of claim 16 , wherein a rate at which each of said plurality of sequence estimation circuits is operable to output bit log-likelihood ratios for said received signal is less than a rate at which bits of said received signal arrive at said receiver.
25 . The system of claim 16 , wherein said digital front-end circuit is operable to add one or more fixed-value padding symbols to each of said plurality of frames.
26 . The system of claim 16 , wherein reset of a state of one of said sequence estimation circuits in response to a particular preamble of a particular one of said plurality of frames comprises:
a determination of a phase of said particular preamble; and
use, by said one of said sequence estimation circuits, of said phase of said particular preamble as an initial phase for processing of symbols of said particular frame.
27 . The system of claim 16 , wherein each of said sequence estimation circuits is operable to equalize a respective one of said plurality of signals.
28 . The system of claim 16 , wherein said digital front-end circuit is operable to equalize said received signal prior to said split of said received signal.