Optoelectronic semiconductor chip and method for fabrication thereof
View Patent ↗An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region. The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
1. An optoelectronic semiconductor chip comprising:
a first semiconductor layer sequence that comprises a plurality of microdiodes; and
a second semiconductor layer sequence that comprises an active region,
wherein the first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material,
wherein the first semiconductor layer sequence is disposed in front of the second semiconductor layer sequence in a growth direction,
wherein the microdiodes form a ESD protection for the active region,
wherein at least 50% of the microdiodes have a breakdown behavior of the same type,
wherein the microdiodes are formed by V-pits, at least 50% of the V-pits having similar dimensions, and
wherein at least one of the microdiodes comprises a pn junction, wherein the active region comprises at least one pn junction, wherein the pn junction of the microdiode and the pn junction of the active region are biased in the same direction, and wherein the pn junction of the microdiode has a lower breakdown voltage (UBR) in a reverse direction than the pn junction of the active region.
2. The optoelectronic semiconductor chip according to claim 1 , wherein at least one of the microdiodes comprises a pn junction, wherein the active region comprises at least one pn junction, wherein the pn junction of the microdiode and the pn junction of the active region are biased in the same direction, and wherein the pn junction of the microdiode has a higher threshold voltage (UF) in a forward direction than the pn junction of the active region.
3. The optoelectronic semiconductor chip according to claim 1 , wherein a density of the microdiodes is at least 5×107/cm2.
4. The optoelectronic semiconductor chip according to claim 1 , wherein at least 75% of the microdiodes are located inside an ESD layer that has a thickness (dg) that is between half and three times a thickness of the active region.
5. The optoelectronic semiconductor chip according to claim 1 , wherein an ESD voltage pulse flows away through at least 50% of the microdiodes in a reverse direction of the microdiodes.
6. The optoelectronic semiconductor chip according to claim 1 , wherein at least 75% of the microdiodes are arranged in a region of a threading dislocation.
7. The optoelectronic semiconductor chip according to claim 1 , wherein the second semiconductor layer sequence directly contacts the first semiconductor layer sequence.
8. The optoelectronic semiconductor chip according to claim 1 , wherein the optoelectronic semiconductor chip is configured to emits blue and/or green light during operation.
9. The optoelectronic semiconductor chip according claim 1 , wherein the optoelectronic semiconductor chip has an ESD strength of at least 1 kV.
10. The optoelectronic semiconductor chip according claim 1 , wherein the microdiodes are formed by V-pits that are arranged entirely in the first semiconductor layer sequence.
11. The optoelectronic semiconductor chip according claim 10 , wherein all V-pits forming the microdiodes are arranged inside an ESD layer.
12. The optoelectronic semiconductor chip according to claim 1 , wherein a density of the V-pits is at least 5×108/cm2 and at most 5×109/cm2.
13. The optoelectronic semiconductor chip according to claim 1 , wherein at least 75% of the microdiodes are located inside an ESD layer that has a thickness of at least 80 nm and at most 150 nm.
14. The optoelectronic semiconductor chip according to claim 1 , wherein at least 75% of the V-pits have similar dimensions.
15. The optoelectronic semiconductor chip according to claim 1 , wherein at least 75% of the V-pits have similar dimensions.
16. An optoelectronic semiconductor chip comprising:
a first semiconductor layer sequence that comprises a plurality of microdiodes; and
a second semiconductor layer sequence that comprises an active region,
wherein the first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material,
wherein the first semiconductor layer sequence is disposed in front of the second semiconductor layer sequence in a growth direction,
wherein the microdiodes form a ESD protection for the active region,
wherein a majority of the microdiodes have a breakdown behavior of the same type,
wherein the microdiodes are formed by V-pits, a majority of the V-pits having similar dimensions,
wherein at least 75% of the microdiodes are located inside an ESD layer that is based on GaN, and wherein the ESD layer was grown at a growth temperature below 900° C. by using a triethylgallium precursor with a nitrogen carrier gas.
17. The optoelectronic semiconductor chip according to claim 1 , wherein the microdiodes do not increase electrical resistance along a breakdown path in the optoelectronic semiconductor chip.
18. The optoelectronic semiconductor chip according to claim 1 , wherein at least one of the microdiodes has an n-side which is n-conducting and a p-side which is p-conducting, and wherein the n-side of the at least one microdiode is arranged in the first semiconductor layer sequence which is n-doped and the p-side is arranged in a p-doped region of the second semiconductor layer sequence.
19. The optoelectronic semiconductor chip according to claim 1 , wherein at least one of the microdiodes comprises a p-n-junction which is arranged in the active region.