MEMORY SYSTEM

1 . A memory system comprising:

a nonvolatile memory;

a controller configured to control the nonvolatile memory; and

a first list and a second list that register address information in the nonvolatile memory,

wherein the controller is configured to

read first data from the nonvolatile memory;

determine whether refresh operation is executed based on the first data read out from the nonvolatile memory;

register address information of the first data into the first list, when refresh operation is determined to be executed;

register the address information registered in the first list into the second list; and

execute refresh operation based on the address information registered in the second list.

2 . The memory system of claim 1 , wherein the controller stands by for a period until the address information registered in the first list is registered into the second list.

3 . The memory system of claim 2 , wherein

the nonvolatile memory comprises at least one memory cell; and

the controller sets the period shorter when a degree of fatigue of the at least one memory cell is determined to be high, and sets the period longer when the degree of fatigue of the at least one memory cell is determined to be low.

4 . The memory system of claim 1 , wherein the first and second lists have queue structures and are used in a series.

5 . The memory system of claim 1 , wherein the controller controls a time when the address information registered in the first list is registered into the second list, based on a degree of fatigue of the nonvolatile memory.

6 . The memory system of claim 1 , wherein the controller registers the address information of the first data into one of the first and second lists, when the refresh operation is executed.

7 . The memory system of claim 6 , wherein the first and second lists have queue structures and are used in a parallel.

8 . The memory system of claim 6 , wherein the controller selects one of the first and second lists, based on whether the first data is importance data, or whether number of error bits is not less than a threshold.

9 . The memory system of claim 6 , wherein the controller determines whether error correction can be executed on the first data.

10 . The memory system of claim 9 , wherein the controller executes shift read operation on the nonvolatile memory when error correction cannot be executed on the first data.

11 . The memory system of claim 10 , wherein the nonvolatile memory is a NAND flash memory comprising a plurality of memory cells.

12 . The memory system of claim 10 , wherein when executing the shift read operation, the controller executes data reading, with a shift amount varied, until the data reading succeeds, or executes data reading, with the shift amount varied, until number of data reads reaches an upper limit.

13 . The memory system of claim 12 , wherein the controller selects one of the first and second lists, based on the shift amount or the shift direction.