Semiconductor memory device

1. A semiconductor memory device comprising:

a memory cell array comprising memory cells each of which is configured to store data of n bits (n is a natural number equal to 2 or more);

a data storage circuit which holds first data to be written into one of the memory cells and also holds 1 bit data calculated from the first data; and

a control circuit which writes the data of n bits into the memory cell in a first write operation and then executes a second write operation,

wherein, in the second write operation, the control circuit reads data stored in the memory cell in the first write operation,

restores the first data based on the data read from the memory cell and the data of 1 bit held in the data storage circuit, and

writes the restored first data into the memory cell.

2. The semiconductor memory device according to claim 1 ,

wherein, when read voltage levels used for write verify of the memory cell in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading of data stored in the memory cell in the second write operation is E (A<E<B).

3. The semiconductor memory device according to claim 1 ,

wherein, when read voltage levels used for write verify of the memory cell in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading data stored in the memory cell in the second write operation is F (B<F<C).

4. The semiconductor memory device according to claim 1 ,

wherein the data storage circuit comprises latch circuits each of which temporarily stores bits, writing of at least data of 1 bit is completed during the first write operation, and second data to be written in a subsequent write operation is temporarily held in a latch circuit that is not used for the first write operation in the latch circuits.

5. The semiconductor memory device according to claim 1 ,

wherein the data storage circuit comprises latch circuits each of which temporarily stores bits, and second data to be written in a subsequent write operation is temporarily held in a latch circuit that is not used for the second write operation in the latch circuits after end of the first write operation or during the second write operation.

6. The semiconductor memory device according to claim 1 ,

wherein, after end of the second write operation, the second write operation is again repeatedly executed.

7. The semiconductor memory device according to claim 1 ,

wherein the memory cells include a first memory cell and a second memory cell,

writing is executed by the first write operation in the order of the first memory cell and the second memory cell connected to a first word line, and

then writing is executed by the second write operation in the order of the first memory cell and the second memory cell.

8. The semiconductor memory device according to claim 1 ,

wherein the memory cells include a first memory cell, a second memory cell, a third memory cell and a fourth memory cell,

writing is executed by the first write operation in the order of the first memory cell and the second memory cell connected to a first word line and the third memory cell and the fourth memory cell connected to a second word line, and

then writing is executed by the second write operation in the order of the first memory cell, the second memory cell, the third memory cell and the fourth memory cell.

9. The semiconductor memory device according to claim 1 ,

wherein the first write operation and second write operation are executed as one program sequence.

10. The semiconductor memory device according to claim 1 ,

wherein the control circuit executes a weak erase operation between the first write operation and the second write operation, and

the control circuit applies a weak erase voltage to the memory cell in the weak erase operation, the weak erase voltage has a reverse voltage for a write voltage applied to the memory cell in the first and second write operations.

11. A semiconductor memory device comprising:

a memory cell array comprising memory cells each of which is configured to store data of n bits (n is a natural number equal to 2 or more);

a data storage circuit which holds first data to be written into one of the memory cells and also holds 1 bit data calculated from the first data; and

a control circuit which writes data of n bits into the memory cell in a first write operation and then executes a second write operation,

wherein, in the second write operation, the control circuit performs verify reading with respect to the memory cell subjected to writing in the first write operation to discriminate a memory cell that has not reached a verify voltage level,

restores the first data based on a result of the discrimination and the data of 1 bit held in the data storage circuit, and

writes the restored first data into the memory cell that has not reached the verify voltage level.

12. The semiconductor memory device according to claim 11 ,

wherein, when read voltage levels used for write verify of the memory cell in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading of data stored in the memory cell in the second write operation is E (A<E<B).

13. The semiconductor memory device according to claim 11 ,

wherein, when read voltage levels used for write verify of the memory cell in the first write operation are A, B, and C (A<B<C), read voltage levels used for reading data stored in the memory cell in the second write operation is F (B<F<C).

14. The semiconductor memory device according to claim 11 ,

wherein the data storage circuit comprises latch circuits each of which temporarily stores bits, writing of at least data of 1 bit is completed during the first write operation, and second data to be written in a subsequent write operation is temporarily held in a latch circuit that is not used for the first write operation in the latch circuits.

15. The semiconductor memory device according to claim 11 ,

wherein the data storage circuit comprises latch circuits each of which temporarily stores bits, and second data to be written in a subsequent write operation is temporarily held in a latch circuit that is not used for the second write operation in the latch circuits after end of the first write operation or during the second write operation.

16. The semiconductor memory device according to claim 11 ,

wherein, after end of the second write operation, the second write operation is again repeatedly executed.

17. The semiconductor memory device according to claim 11 ,

wherein the memory cells include a first memory cell and a second memory cell,

writing is executed by the first write operation in the order of the first memory cell and the second memory cell connected to a first word line, and

then writing is executed by the second write operation in the order of the first memory cell and the second memory cell.

18. The semiconductor memory device according to claim 11 ,

wherein the memory cells include a first memory cell, a second memory cell, a third memory cell and a fourth memory cell,

writing is executed by the first write operation in the order of the first memory cell and the second memory cell connected to a first word line and the third memory cell and the fourth memory cell connected to a second word line, and

then writing is executed by the second write operation in the order of the first memory cell, the second memory cell, the third memory cell and the fourth memory cell.

19. The semiconductor memory device according to claim 11 ,

wherein the first write operation and second write operation are executed as one program sequence.

20. The semiconductor memory device according to claim 11 ,

wherein the control circuit executes a weak erase operation between the first write operation and the second write operation, and

the control circuit applies a weak erase voltage to the memory cell in the weak erase operation, the weak erase voltage has a reverse voltage for a write voltage applied to the memory cell in the first and second write operations.