IP Library Granted Patent US 9,654,801
Granted Patent B2
US 9,654,801 · App. 14/689,225 · Granted May 16, 2017

Advanced video coding and decoding chip and advanced video coding and decoding method

Inventor: ChuanChuan Zhu (Shanghai, CN)
Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
H04N19/625H04N19/436H04N19/61
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Quick Facts
Patent No.
US 9,654,801
App. No.
14/689,225
Granted
May 16, 2017
Kind
B2
Abstract

An advanced video coding and decoding chip and a method with a hardware design that calculates direct current coefficients in discrete-cosine-transformed residual blocks corresponding to sixteen sub-blocks within a macroblock and alternating current coefficients in the discrete-cosine-transformed residual blocks corresponding to the sixteen sub-blocks within the macroblock separately and in parallel.

Claims (30)

1. An advanced video coding and decoding chip, comprising:

direct current coefficient evaluation hardware, evaluating direct current coefficients in discrete-cosine-transformed residual blocks corresponding to sixteen sub-blocks within a macroblock, each sub-block containing 4×4 pixels;

Hadamard transform hardware, performing a Hadamard transform on the direct current coefficients corresponding to the sixteen sub-blocks to generate Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks;

alternating current coefficient evaluation hardware, evaluating alternating current coefficients in the discrete-cosine-transformed residual blocks corresponding to the sixteen sub-blocks; and

quantization hardware, performing quantization on the Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks and performing quantization on the alternating current coefficients corresponding to the sixteen sub-blocks to generate transform coefficients corresponding to the sixteen sub-blocks,

wherein the direct current coefficient evaluation hardware performs a calculation, DC k =Σ i=0 3 Σ j=0 3 (X k ) ij , where k=0 . . . 15, X k is a residual block corresponding to one of the sixteen 4×4 sub-blocks and DC k is the corresponding direct current coefficient;

wherein the alternating current coefficient evaluation hardware performs a calculation, M 1 ·X k ·M 2 to get the alternating current coefficients, where M 1 and M 2 are a first 4×4 matrix and a second 4×4 matrix for a discrete-cosine-transform;

wherein the Hadamard transform hardware starts the Hadamard transform on the direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks; and

wherein the Hadamard transform hardware further finishes the Hadamard transform on the direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

2. The advanced video coding and decoding chip as claimed in claim 1 , wherein:

the quantization hardware starts the quantization on the Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

3. The advanced video coding and decoding chip as claimed in claim 2 , wherein:

the quantization hardware finishes the quantization on the Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

4. The advanced video coding and decoding chip as claimed in claim 3 , further comprising:

an inverse quantization and inverse discrete cosine transform hardware, starting inverse quantization and inverse discrete cosine transform on the transform coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

5. A method for advanced video coding and decoding, comprising:

using direct current coefficient evaluation hardware to evaluate direct current coefficients in discrete-cosine-transformed residual blocks corresponding to sixteen 4×4 sub-blocks within a macroblock;

using Hadamard transform hardware to perform a Hadamard transform on the direct current coefficients corresponding to the sixteen sub-blocks to generate Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks;

using alternating current coefficient evaluation hardware to evaluate alternating current coefficients in the discrete-cosine-transformed residual blocks corresponding to the sixteen sub-blocks; and

using quantization hardware to perform quantization on the Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks and quantization on the alternating current coefficients corresponding to the sixteen sub-blocks to generate transform coefficients corresponding to the sixteen sub-blocks,

wherein the direct current coefficient evaluation hardware is operated to perform a calculation, DC k =Σ i=0 3 Σ j=0 3 (X k ) ij , where k=0 . . . 15, X k is a residual block corresponding to one of the sixteen 4×4 sub-blocks and DC k is the conesrrsponding direct current coefficient;

wherein the alternating current coefficient evaluation hardware is operated to perform a calculation,M 1 ·X k ·M 2 to get the alternating current coefficients, where M 1 and M 2 are a first 4×4 matrix and a second 4×4 matrix for a discrete-cosine-transform;

wherein the Hadamard transform hardware starts the Hadamard transform on the direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks; and

wherein the Hadamard transform hardware further finishes the Hadamard transform on the direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

6. The advanced video coding and decoding method as claimed in claim 5 , wherein:

the quantization hardware starts the quantization on the Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

7. The advanced video coding and decoding method as claimed in claim 6 , wherein:

the quantization hardware finishes the quantization on the Hadamard-transformed direct current coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

8. The advanced video coding and decoding method as claimed in claim 7 , further comprising:

using an inverse quantization and inverse discrete cosine transform hardware to start inverse quantization and inverse discrete cosine transform on the transform coefficients corresponding to the sixteen sub-blocks before the alternating current coefficient evaluation hardware completely evaluates the alternating current coefficients corresponding to the sixteen sub-blocks.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2021
From: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
To: GLENFLY TECH CO., LTD.
Reel/Frame 058965/0042 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2015
From: ZHU, CHUANCHUAN
To: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
Reel/Frame 035433/0509 →
Priority Claims (1)
CN 2014 1 0766061 · Dec 11, 2014 · national
Continuity (1)
Related Publication 20160173908A1 · Jun 16, 2016