IP Library Granted Patent US 9,437,912
Granted Patent B2
US 9,437,912 · App. 14/691,552 · Granted Sep 6, 2016

3-D integrated package

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Quick Facts
Patent No.
US 9,437,912
App. No.
14/691,552
Granted
Sep 6, 2016
Kind
B2
Abstract

In an example embodiment, an electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.

Claims (41)

1. An electronics package comprising:

a plurality of transition layers, each transition layer including:

an insulating layer;

a signal via configured to pass through the insulating layer and that is electrically coupled with the signal via of an adjacent transition layer;

a ground plane having a signal cut configured to provide clearance between the ground plane and the signal via; and

a plurality of ground vias each configured to electrically couple the ground plane of the transition layer with the ground plane of an adjacent transition layer; and

an electrically conductive transmission line including:

a coplanar waveguide portion electrically coupled to a microstrip portion;

the signal vias of the plurality of transition layers; and

a signal pin electrically coupled to the signal vias, wherein the signal pin is configured to be electrically coupled to a printed circuit board (PCB) via a PCB signal trace deposited on the PCB.

2. The electronics package of claim 1 , wherein the signal via of the insulating layer and the signal via of the adjacent transition layer are staggered.

3. The electronics package of claim 1 , wherein the signal via of the insulating layer and the signal via of the adjacent transition layer are axially aligned.

4. The electronics package of claim 1 , further comprising a capacitor electrically coupled to the microstrip portion.

5. The electronics package of claim 4 , further comprising a ground plane adjacent to the capacitor, the adjacent ground plane including a capacitor ground cut adjacent to the capacitor.

6. The electronics package of claim 1 , wherein the ground plane is located at a face of the insulating layer.

7. The electronics package of claim 1 , further comprising a ground plane adjacent to a package-PCB interface, the adjacent ground plane including a transition ground cut configured to provide clearance between the adjacent ground plane and the signal pin.

8. The electronics package of claim 7 , wherein the transition ground cut is located at an edge of the adjacent ground plane.

9. The electronics package of claim 7 , wherein the transition ground cut is substantially rectangular.

10. The electronics package of claim 1 , wherein the signal cuts are substantially circular.

11. The electronics package of claim 1 , wherein the electronics package includes a ceramic material.

12. A high-speed transponder comprising a printed circuit board (PCB) electrically coupled to the electronics package of claim 1 and an optoelectronic circuit package.

13. Multiple component circuitry comprising:

a printed circuit board (PCB);

a PCB signal trace deposited on the PCB; and

an electronics package including:

a plurality of transition layers, each transition layer including:

an insulating layer;

a signal via configured to pass through the insulating layer and that is electrically coupled with the signal via of an adjacent transition layer;

a ground plane having a signal cut configured to provide clearance between the ground plane and the signal via; and

a plurality of ground vias each configured to electrically couple the ground plane of the transition layer with the ground plane of an adjacent transition layer; and

an electrically conductive transmission line including:

a coplanar waveguide portion electrically coupled to a microstrip portion;

the signal vias of the plurality of transition layers; and

a signal pin electrically coupled to the signal vias and electrically coupled to the PCB via the PCB signal trace.

14. The multiple component circuitry of claim 13 , further comprising an optoelectronic circuit package electrically coupled to the PCB via the PCB signal trace.

15. The multiple component circuitry of claim 14 , wherein the signal via of the insulating layer and the signal via of the adjacent transition layer are staggered.

16. The multiple component circuitry of claim 14 , wherein the signal via of the insulating layer and the signal via of the adjacent transition layer are axially aligned.

17. The multiple component circuitry of claim 14 , the electronics package further including a capacitor electrically coupled to the microstrip portion.

18. The multiple component circuitry of claim 17 , the electronics package further including a ground plane adjacent to the capacitor, the adjacent ground plane including a capacitor ground cut adjacent to the capacitor.

19. The multiple component circuitry of claim 14 , the electronics package further including a ground plane adjacent to a package-PCB interface, the adjacent ground plane including a transition ground cut configured to provide clearance between the adjacent ground plane and the signal pin.

20. The multiple component circuitry of claim 14 , wherein the signal cuts are substantially circular.

Assignments (5)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2015
From: SONG, YUNPENG; LIU, YONGSHENG; DENG, HONGYU
To: FINISAR CORPORATION
Reel/Frame 036830/0992 →