Method of manufacturing isolation structure and non-volatile memory with the isolation structure
A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
1. A method of manufacturing an isolation structure, comprising:
providing a substrate;
sequentially forming a dielectric layer, a conductive layer, and a hard mask layer on the substrate;
patterning the hard mask layer and the conductive layer to form a first trench exposing the dielectric layer;
forming a first liner on the substrate;
removing the first liner and the dielectric layer exposed by the first trench, so as to expose the substrate and form a spacer on a sidewall of the conductive layer and a sidewall of the hard mask layer, respectively, wherein the spacer is formed from the first liner;
removing a portion of the substrate to form a second trench by using the conductive layer and the hard mask layer having the spacer as a mask; and
forming an isolation layer in the second trench, wherein a distance between the conductive layers is greater than a width of the second trench,
wherein the step of forming the isolation layer in the second trench comprises:
forming a second liner in the second trench;
performing an annealing process;
filling the second trench with an insulation material layer; and
performing a curing process.
2. The method of claim 1 , wherein a method of forming the first liner comprises an in-situ steam generation method, a thermal oxidation method, or an atomic layer deposition method.
3. The method of claim 1 , wherein a material of the dielectric layer comprises silicon oxide.
4. The method of claim 1 , wherein a material of the conductive layer comprises a doped polysilicon layer and a non-doped polysilicon layer.
5. The method of claim 1 , wherein a material of the hard mask layer comprises silicon nitride or silicon oxide.
6. The method of claim 1 , wherein a material of the first liner comprises silicon oxide.
7. The method of claim 1 , wherein a material of the insulation material layer comprises a spin-on dielectric material.
8. The method of claim 1 , wherein a material of the second liner comprises silicon oxide.
9. A method of manufacturing a non-volatile memory, comprising:
providing a substrate, a dielectric layer, a first conductive layer, and a hard mask layer being sequentially formed on the substrate;
patterning the hard mask layer and the first conductive layer to form a first trench exposing the dielectric layer;
forming a first liner on the substrate;
removing the first liner and the dielectric layer exposed by the first trench, so as to expose the substrate and form a spacer on a sidewall of the first conductive layer and a sidewall of the hard mask layer, respectively, wherein the spacer is formed from the first liner;
removing a portion of the substrate to form a second trench by using the first conductive layer and the hard mask layer having the spacer as a mask;
forming an isolation layer in the second trench, wherein a distance between the first conductive layers is greater than a width of the second trench, wherein the step of forming the isolation layer in the second trench comprises:
forming a second liner in the second trench;
performing an annealing process;
filling the second trench with an insulation material layer; and
performing a curing process;
removing the hard mask layer;
Ruining an inter-gate dielectric layer on the substrate;
forming a second conductive layer on the inter-gate dielectric layer; and
patterning the second conductive layer, the inter-gate dielectric layer, and the first conductive layer to form a control gate and a floating gate.
10. The method of claim 9 , wherein the first conductive layer comprises a doped polysilicon layer and a non-doped polysilicon layer.
11. The method of claim 9 , wherein a method of forming the first liner comprises an in-situ steam generation method, a thermal oxidation method, or an atomic layer deposition method.
12. The method of claim 9 , wherein a material of the dielectric layer comprises silicon oxide.
13. The method of claim 9 , wherein a material of the hard mask layer comprises silicon nitride or silicon oxide.
14. The method of claim 9 , wherein a material of the first liner comprises silicon oxide.
15. The method of claim 9 , wherein a material of the inter-gate dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.
16. The method of claim 9 , wherein a material of the second conductive layer comprises doped polysilicon.