Semiconductor integrated circuit device and multi chip package including the same

1. A semiconductor integrated circuit device, comprising:

a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode; and

a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode,

wherein the first circuit block is configured to be connected to the plurality of data I/O lines, multiplex the data of the plurality of data I/O lines and output the multiplexed data as the test data in response to column addresses, and

wherein the second circuit block comprises an output unit transmit the test data to selected pads of I/O pads in the test mode.

2. The semiconductor integrated circuit device according to claim 1 , wherein the second circuit block further comprises:

a selection unit configured to be connected to two or more data I/O lines, select the data received from the two or more of data I/O lines in the normal mode and select the test data provided from the first circuit block in the test mode; and

wherein the output unit is configured to be connected to the plurality of data I/O lines, transmit data of the plurality of data I/O lines to the I/O pads in the normal mode.

3. The semiconductor integrated circuit device according to claim 2 , wherein the output unit includes a plurality of control buffers connected to the plurality of data I/O lines.

4. The semiconductor integrated circuit device according to claim 3 , wherein a selected one of the control buffers receives the test data, the selected control buffer receiving the test data is enabled and all remaining control buffers are disabled in the test mode.

5. The semiconductor integrated circuit device according to claim 1 , further comprising a blocking unit configured to block the transmission of the data of the plurality of data I/O lines in the test mode.

6. A multi chip package, comprising:

a first chip including first I/O(input/output) pads; and

a second chip including second I/O pads, stacked on the first chip,

wherein at least one of the first and second chips comprises:

a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output test data in a test mode; and

a second circuit block configured to connect the plurality of data I/O lines and the first circuit block, output the data of the plurality of data I/O lines in a normal mode and output the test data provided from the first circuit block in the test mode,

wherein the first circuit block is configured to be connected to the plurality of data I/O lines, multiplex the data of the plurality of data I/O lines and output the multiplexed data as the test data in response to column addresses, and

wherein the second circuit block comprises an output unit transmit the test data to selected pads of the I/O pads in the test mode.

7. The multi chip package according to claim 6 , wherein the first circuit block comprises a plurality of MUXes configured to classify the plurality of data I/O lines into some groups, and each configured to output one of the data loaded onto some of the data I/O lines, corresponding to one of the groups, as one of the test data in response to column addresses.

8. The multi chip package according to claim 7 , wherein the second circuit block comprises:

a selection unit configured to be connected to two or more data I/O lines, select the data received from the two or more of data I/O lines in the normal mode and select the test data provided from the first circuit block in the test mode; and

the output unit further configured to be connected to the plurality of data I/O lines, transmit data of the plurality of data I/O lines to I/O pads in the normal mode.

9. The multi chip package according to claim 8 ,

wherein the selection unit includes a plurality of sub selection units receiving the respective test data from a plurality of the MUXes.

10. The multi chip package according to claim 8 , wherein the output unit includes a plurality of control buffers connected to the plurality of data I/O lines.

11. The multi chip package according to claim 10 , wherein a selected one of the control buffers receives the test data, the selected control buffer receiving the test data is enabled and all remaining control buffers are disabled in the test mode.

12. The multi chip package according to claim 6 , further comprising a control unit configured to generate an output enable signal and a test output enable signal in response to a test mode signal.

13. The multi chip package according to claim 12 ,

wherein the control unit comprises:

a chip selection signal generator configured to decode the pieces of chip information into a plurality of chip selection signals; and

an output enable signal generator configured to generate the output enable signal and the test output enable signal, corresponding to the respective chip selection signals, in response to the plurality of chip selection signals and the test mode signal.

14. The multi chip package according to claim 13 , wherein the chip selection signal generator activates a chip selection signal corresponding to a relevant memory chip, from among the plurality of chip selection signals.

15. The multi chip package according to claim 13 , wherein the output enable signal generator activates all the output enable signal and the test output enable signal, when the test mode signal is deactivated, and

the output enable signal generator deactivates the output enable signal and activates the test output enable signal in response to an activation state of each of the chip selection signals, when the test mode signal is activated.

16. The multi chip package according to claim 6 , further comprising a blocking unit configured to block the transmission of the data of the plurality of data I/O lines in the test mode.

17. The multi chip package according to claim 6 , wherein the first I/O pads and the second I/O pads are electrically coupled by TSVs (through silicon vias).