Optimization of loops and data flow sections in multi-core processor environment
The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
1. A microprocessor on a chip comprising:
a plurality of arithmetic units;
a register file comprising a plurality of data registers communicatively connected to the plurality of arithmetic units; and
an instruction fetcher and instruction decoder supplying instructions of one or more software threads to the plurality of arithmetic units;
wherein the microprocessor is capable of executing the one or more software threads in at least one mode of a plurality of modes, the plurality of modes including:
i) the arithmetic units are operating jointly on one of the one or more software threads using a single program pointer; and
ii) a plurality of groups of arithmetic units are operating on different software threads of the one or more software threads using a plurality of program pointers,
each group of arithmetic units having one of the plurality of program pointers dedicated to that group of arithmetic units;
wherein the microprocessor further comprises a plurality of instruction decode units supplying instructions to the plurality of arithmetic units according to the single program pointer or the plurality of program pointers.
2. The microprocessor according to claim 1 , wherein the plurality of arithmetic units are arranged in an array.
3. The microprocessor according to claim 2 , wherein a network interconnects the plurality of arithmetic units in the array.
4. The microprocessor according to claim 2 , wherein while executing the one or more software threads in a loop, at least a plurality of the instructions stay the same for a plurality of clock cycles once supplied to the arithmetic units while multiple data words are streamed through the arithmetic units and processed by the arithmetic units based on the at least a plurality of the instructions.
5. The microprocessor according to claim 1 , wherein in mode (ii) the register file is split, providing a dedicated register space to each group of arithmetic units operating on a different thread.
6. A method for operating a microprocessor on a chip, the method comprising:
providing a plurality of arithmetic units and a register file comprising a plurality of data
registers communicatively connected to the plurality of arithmetic units;
providing an instruction fetcher and instruction decoder to supply instructions of one or more software threads to the plurality of arithmetic units; and
executing the one or more software threads in at least one mode of a plurality of modes, the plurality of modes including:
i) the arithmetic units are operating jointly on one of the one or more software threads using a single program pointer; and
ii) a plurality of groups of arithmetic units are operating on different software threads of the one or more software threads using a plurality of program pointers,
each group of arithmetic units having one of the plurality of program pointers dedicated to that group of arithmetic units;
further comprising supplying instructions to the plurality of arithmetic units according to the single program pointer or the plurality of program pointers using a plurality of instruction decode units.
7. The method according to claim 6 , wherein the plurality of arithmetic units are arranged in an array.
8. The method according to claim 7 , wherein a network interconnects the plurality of arithmetic units in the array.
9. The method according to claim 7 , wherein while executing the one or more software threads in a loop, at least a plurality of the instructions stay the same for a plurality of clock cycles once supplied to the arithmetic units while multiple data words are streamed through the arithmetic units and processed by the arithmetic units based on the at least a plurality of the instructions.
10. The method according to claim 6 , wherein in mode (ii) the register file is split, providing a dedicated register space to each group of arithmetic units operating on a different thread.