IP Library Granted Patent US 9,535,661
Granted Patent B2
US 9,535,661 · App. 14/693,801 · Granted Jan 3, 2017

Method and device for removing biasing due to signal source during random number generation

Inventors: Jeong-sik Cho (Daejeon, KR); Jeong-woon Choi (Yongin-si, KR)
Assignee: SK TELECOM CO., LTD.
G06F7/588G06F7/58G06F7/76
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Quick Facts
Patent No.
US 9,535,661
App. No.
14/693,801
Granted
Jan 3, 2017
Kind
B2
Abstract

The present disclosure provides a method and an apparatus for removing biasing due to a signal source during random number generation. At least one embodiment includes a method, performed by a random number generation apparatus, for generating a random number having a signal source biasing removed, including: generating a raw bit string by sampling, at a predetermined cycle, a physical signal input from a signal source; and generating the random number by performing block partial sum or sequential partial sum on the generated raw bit string.

Claims (46)

1. A method, performed by a random number generation apparatus, for generating a random number having a signal source biasing removed, the method comprising:

generating a raw bit string by sampling, at a predetermined cycle, a physical signal input from a signal source; and

generating the random number by performing sequential partial sum on the generated raw bit string,

wherein the sequential partial sum indicates each partial sum calculated by shifting a selection range of sample values by one bit when a predetermined number of partial sums are selected from among the generated raw bit string.

2. The method of claim 1 , wherein the generating of the raw bit string comprises comparing a sample value from the sampling with a predetermined reference value to generate the raw bit string.

3. The method of claim 1 , wherein the performing sequential partial sum comprises:

applying a mask of a predetermined size to the raw bit string to calculate a parity bit; and

calculating a next parity bit while moving the mask at least one bit from a point where a current parity bit is generated.

4. The method of claim 1 , further comprising removing deviation in the input physical signals, prior to the sampling.

5. The method of claim 4 , wherein the removing of the deviation comprises removing the deviation by using one of a direct current (DC) filter and an automatic deviation compensation circuit.

6. A method, performed by a random number generation apparatus, for generating a random number having a signal source biasing removed, the method comprising:

generating raw bit strings for respective physical signals by sampling the physical signals input from a plurality of signal sources, at a predetermined cycle;

generating a plurality of parity bit strings by performing block partial sum or sequential partial sum on the respective raw bit strings; and

generating the random number by sequentially arranging parity bits included in the plurality of parity bit strings in a generation sequence of the parity bits,

wherein the block partial sum is calculated for checking whether the number of “1” bits or “0” bits in each block is an even number or an odd number, where said each block is divided from the generated raw bit string and includes a predetermined number of bits, and

the sequential partial sum indicates each partial sum calculated by shifting a selection range of sample values by one bit when a predetermined number of partial sums are selected from among the generated raw bit string.

7. The method of claim 6 , further comprising removing deviation included in the input physical signal, prior to the sampling.

8. The method of claim 7 , wherein the removing of the deviation comprises removing the deviation by using one of a direct current (DC) filter and an automatic deviation compensation circuit.

9. An apparatus for generating a random number having a signal source biasing removed, the apparatus comprising:

a signal source configured to generate a physical signal as a basis for generating the random number;

a clock generator configured to generate a clock having a predetermined frequency;

a sampler configured to output a bit value of 0 or 1 according to a result obtained by comparing a value from sampling the physical signal with a predetermined reference value at each clock; and

a calculator configured to perform sequential partial sum on a bit string as an output of the sampler to generate the random number,

wherein the sequential partial sum indicates each partial sum calculated by shifting a selection range of sample values by one bit when a predetermined number of partial sums are selected from among the generated raw bit string.

10. The apparatus of claim 9 , further comprising one of a direct current (DC) filter and an automatic deviation compensation circuit, the one of the DC filter and the automatic gain circuit are configured to remove deviation of the physical signal,

wherein the sampler is further configured to sample an output signal of the one of the DC filter and the automatic deviation compensation circuit.

11. An apparatus for generating a random number having a signal source biasing removed, the apparatus comprising:

a plurality of random number generators, each configured to generate a raw bit string from physical phenomena; and

a calculator configured to:

generate a plurality of parity bit strings by performing block partial sum or sequential partial sum on the respective raw bit strings generated by the plurality of random number generators, and

generate a random number sequence by sequentially arranging respective parity bits included in the plurality of parity bit strings in a generation sequence of the parity bits,

wherein the block partial sum is calculated for checking whether the number of “1” bits or “0” bits in each block is an even number or an odd number, where said each block is divided from the generated raw bit string and includes a predetermined number of bits, and

the sequential partial sum indicates each partial sum calculated by shifting a selection range of sample values by one bit when a predetermined number of partial sums are selected from among the generated raw bit string.

12. The apparatus of claim 11 , wherein each random number generator comprises:

a signal source configured to generate a physical signal as a basis for generating the random number;

a clock generator configured to generate a clock having a predetermined frequency; and

a sampler configured to output a bit value of 0 or 1 according to a result obtained by comparing a value from sampling the physical signal with a predetermined reference value at each clock.

13. The apparatus of claim 12 , wherein each of the random number generators further comprises:

a compensation control circuit configured to:

analyze deviation from a value obtained from the sampling and

feedback to the sampler a feedback signal for removing the deviation.

14. A method, performed by a random number generation apparatus, for generating a random number having a signal source biasing removed, the method comprising:

generating raw bit strings for respective physical signals by sampling the physical signals input from a plurality of signal sources, at a predetermined cycle;

generating a plurality of parity bit strings by performing sequential partial sum on the respective raw bit strings; and

generating the random number by sequentially arranging parity bits included in the plurality of parity bit strings in a generation sequence of the parity bits,

wherein the sequential partial sum indicates each partial sum calculated by shifting a selection range of sample values by one bit when a predetermined number of partial sums are selected from among the generated raw bit string.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2018
From: SK TELECOM CO., LTD.
To: ID QUANTIQUE
Reel/Frame 047859/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2015
From: CHO, JEONG-SIK; CHOI, JEONG-WOON
To: SK TELECOM CO., LTD.
Reel/Frame 035474/0617 →
Priority Claims (1)
KR 10-2012-0118558 · Oct 24, 2012 · national
Continuity (2)
Continuation PCTKR2013007509 · Aug 21, 2013
Related Publication 20150227345A1 · Aug 13, 2015