Thin film transistor and display device
View Patent ↗For improved high-definition of liquid crystal display devices and the use thereof in bright places, luminance of backlights is being increased. Thus, when a light-shielding layer is employed for suppressing a light leakage current, characteristic fluctuations of transistors are caused, which may result in showing faulty display. In a dual-gate thin film transistor having a floating light-shielding layer, the layout is designed in such a manner that the film thickness of the insulating layer is equal to or more than 200 nm and equal to or less than 500 nm and that Sg/Sd becomes 4.7 or more, provided that an opposing area between the light-shielding layer and a drain region in a place at the outermost side of the active layer is Sd and the opposing area between the light-shielding layer and the gate electrode is Sg.
1. A thin film pixel transistor having a dual-gate structure, comprising:
a channel region, a LDD region, and a drain region formed with a polycrystalline silicon active layer,
said active layer having a uniform thickness in the channel region and the LDD region, and having a protruded part of a corner of a step that is thinner than the channel region caused by surface tension, the step being formed by an electrically floating light-shielding layer; and
gate electrodes provided at least in the channel region via a gate insulating film,
the electrically floating light-shielding layer overlapping at least the channel region and the LDD region via an insulating layer,
wherein a border is provided between the channel region and the LDD region,
wherein a film thickness of the insulating layer is equal to or more than 200 nm and equal to or less than 500 nm, the channel region and the LDD region including concave portions along edges of the electrically floating light-shielding layer, and the border and the step are parallel with each other in plan view,
wherein the dual-gate structure of the thin film transistor is constituted by a first transistor and a second transistor, the electrically floating light-shielding layer being electrically separated for each one of the first and second transistors,
wherein, for the first and second transistors, an opposing area in plan view of the drain region and the electrically floating light-shielding layer is Sd, an opposing area in plan view of the gate electrode and the electrically floating light-shielding layer is Sg, and a G/D ratio is a ratio Sg/Sd, and
wherein a first of the two transistors has a larger G/D ratio than that of the second of the two transistors, and said first of the two transistors is directly connected to a pixel electrode.