ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES
A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
1 . A semiconductor device, comprising:
a substrate having a plurality of regions including a first region and a second region;
a first gate structure formed in the first region including a first dielectric layer, which has a top layer, middle layer, and bottom layer of the first dielectric layer, the top layer of the first dielectric layer including hafnium (Hf), lanthanum (La), oxygen (O), and nitrogen (N), the middle layer of the first dielectric layer including La, silicon (Si), O, and N, and the bottom layer of the first dielectric layer including undoped silicon dioxide; and
a second gate structure formed in the second region including a second dielectric layer, which has a top layer, middle layer, and bottom layer of the second dielectric layer, the top layer of the second dielectric layer including Hf, O, and N, the middle layer of the second dielectric layer including Si, O, and N, and the bottom layer of the second dielectric layer including undoped silicon dioxide.
2 . The semiconductor device as recited in claim 1 , wherein the first and second dielectric layers are U-shaped.
3 . The semiconductor device as recited in claim 1 , wherein vertical portions of the first and second gate dielectric layers contact inner portions of sidewall spacers.
4 . The semiconductor device as recited in claim 1 , wherein the first gate structure includes a second work function material, and the second gate structure includes a first and the second work function material.
5 . The semiconductor device as recited in claim 1 , wherein the first and second gate structures include a conductive material.
6 . The semiconductor device as recited in claim 5 , wherein the first gate structure forms an n-type field effect transistor and the second gate structure forms a p-type field effect transistor.
7 . A semiconductor device, comprising:
a first gate structure formed in a first region of a substrate including a first dielectric layer, which has a top layer, middle layer, and bottom layer of the first dielectric layer, the top layer of the first dielectric layer hafnium (Hf), lanthanum (La), oxygen (O), and nitrogen (N), the middle layer of the first dielectric layer including La, silicon (Si), O, and N, wherein hafnium is not present in the middle dielectric layer, and the bottom layer of the first dielectric layer including silicon dioxide; and
a second gate structure formed in a second region of the substrate including a second dielectric layer, which has a top layer, middle layer, and bottom layer of the second dielectric layer, the top layer of the second dielectric layer including Hf, O, and N, the middle layer of the second dielectric layer including Si, O, and N, wherein Hf is not present in the middle dielectric layer, and the bottom layer of the second dielectric layer including silicon dioxide.
8 . The semiconductor device as recited in claim 7 , wherein the first and second dielectric layers are U-shaped.
9 . The semiconductor device as recited in claim 7 , wherein vertical portions of the first and second gate dielectric layers contact inner portions of sidewall spacers.
10 . The semiconductor device as recited in claim 7 , wherein the first gate structure includes a second work function material, and the second gate structure includes a first and the second work function material.
11 . The semiconductor device as recited in claim 7 , wherein the first and second gate structures include a conductive material.
12 . The semiconductor device as recited in claim 11 , wherein the first gate structure forms an n-type field effect transistor and the second gate structure forms a p-type field effect transistor.
13 . The semiconductor device of claim 12 , wherein the n-type field effect transistor is present on a first portion of a substrate that is separated from a second portion of the substrate containing the p-type field effect transistor by an isolation region.
14 . A semiconductor device, comprising:
a first gate structure of an n-type field effect transistor formed in a first region of a substrate including a first dielectric layer, which has a top layer, middle layer, and bottom layer of the first dielectric layer, the top layer of the first dielectric layer including hafnium (Hf), lanthanum (La), oxygen (O), and nitrogen (N), the middle layer of the first dielectric layer including La, silicon (Si), O, and N, and the bottom layer of the first dielectric layer including undoped silicon dioxide; and
a second gate structure of a p-type field effect transistor formed in a second region of a substrate including a second dielectric layer, which has a top layer, middle layer, and bottom layer of the second dielectric layer, the top layer of the second dielectric layer including Hf, O, and N, the middle layer of the second dielectric layer including Si, O, and N, and the bottom layer of the second dielectric layer including undoped silicon dioxide.
15 . The semiconductor device as recited in claim 14 , wherein the first and second dielectric layers are U-shaped.
16 . The semiconductor device as recited in claim 14 , wherein vertical portions of the first and second gate dielectric layers contact inner portions of sidewall spacers.
17 . The semiconductor device as recited in claim 14 , wherein the first gate structure includes a second work function material, and the second gate structure includes a first and the second work function material.
18 . The semiconductor device as recited in claim 17 , wherein the first and second gate structures include a conductive material.
19 . The semiconductor device of claim 14 , wherein the first dielectric layer includes said bottom undoped layer of silicon oxide (SiO 2 ), said middle layer of LaSiON, and said top layer of HfLaON.
20 . The semiconductor device of claim 14 , wherein the second dielectric layer includes said bottom undoped layer of silicon oxide (SiO 2 ), said middle layer of SiON, and said top layer of HfON.