Systems and methods for side-track aided data recovery

1. A data processing system, the system comprising:

an analog to digital converter circuit operable to convert an analog input into a series of digital samples;

an inter-track interference mitigation circuit operable to reduce inter-track interference from the series of digital samples to yield a corrected series of samples;

an equalizer circuit operable to apply an equalization algorithm to the corrected series of samples to yield an equalized output; and

a data processing circuit operable to apply a combination of a data detection algorithm and a data decoding algorithm to the equalized output to yield an originally written data set.

2. The system of claim 1 , wherein the inter-track interference mitigation circuit comprises:

a filter circuit operable to filter a data set derived from a track adjacent to the track from which the analog input is derived to yield inter-track interference values corresponding to the analog input; and

a summation circuit operable to subtract the inter-track interference values from the series of digital samples to yield the corrected series of samples.

3. The system of claim 2 , wherein the filter circuit is a digital finite impulse response circuit governed by a plurality of filter taps.

4. The system of claim 2 , wherein the data set derived from the track adjacent to the track from which the analog input is derived is selected from a group consisting of: an x-sample data set, and a y-sample data set.

5. The system of claim 2 , wherein the data set derived from the track adjacent to the track from which the analog input is derived is generated by re-reading the track adjacent to the track from which the analog input is derived.

6. The system of claim 2 , wherein the data set derived from the track adjacent to the track from which the analog input is derived is generated by buffering data generated during prior processing of the data set derived from the track adjacent to the track from which the analog input is derived.

7. The system of claim 1 , wherein the equalizer circuit is a digital finite impulse response circuit.

8. The system of claim 1 , wherein the equalizer circuit is a recursive equalizer circuit including a buffer circuit operable to hold a previous equalized output.

9. The system of claim 1 , wherein the analog input is a first analog input derived from a first read sensor, wherein the series of digital samples is a first series of digital samples, wherein the analog to digital converter circuit is a first analog to digital converter circuit, wherein the inter-track interference mitigation circuit is a first inter-track interference mitigation circuit, wherein the corrected series of samples is a first corrected series of samples, the system further comprising:

a second analog to digital converter circuit operable to convert a second analog input derived from a second read sensor into a second series of digital samples;

a second inter-track interference mitigation circuit operable to reduce inter-track interference from the second series of digital samples to yield a second corrected series of samples; and

wherein the equalizer circuit is a joint equalizer circuit operable to apply a joint equalization algorithm to a combination of the first corrected series of samples and the second corrected series of samples to yield the equalized output.

10. The system of claim 9 , wherein:

the first inter-track interference mitigation circuit includes:

a first filter circuit operable to filter a data set derived from a track adjacent to the track from which the first analog input is derived to yield a first set of inter-track interference values corresponding to the first analog input, wherein operation of the first filter circuit is governed at least in part by a first set of filter taps; and

a first summation circuit operable to subtract the first set of inter-track interference values from the first series of digital samples to yield the first corrected series of samples; and

the second inter-track interference mitigation circuit includes:

a second filter circuit operable to filter the data set derived from the track adjacent to the track from which the first analog input is derived to yield a second set of inter-track interference values corresponding to the second analog input, wherein operation of the second filter circuit is governed at least in part by a second set of filter taps; and

a second summation circuit operable to subtract the second set of inter-track interference values from the second series of digital samples to yield the second corrected series of samples.

11. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.

12. The system of claim 1 , wherein the system is incorporated in a hard disk drive including a storage medium that includes a track from which the analog input is derived, and an adjacent track that is adjacent to the track from which the analog input is derived.

13. The system of claim 1 , wherein the inter-track interference mitigation circuit is operable to reduce inter-track interference from the series of digital samples by calculating first estimated inter-track interference values from a first side of a target track and second estimated inter-track interference values from a second side of a target track to yield a corrected series of samples.

14. A data storage device, the data storage device comprising:

a storage medium;

a read/write head assembly disposed in relation to the storage medium;

an analog to digital converter circuit operable to convert an information set from target track on the storage medium via the read/write head assembly into a sample set;

an inter-track interference mitigation circuit operable to reduce inter-track interference from the sample set to yield a corrected series of samples; and

a read channel circuit including:

an equalizer circuit operable to equalize the corrected series of samples to yield a data input;

a data detector circuit operable to apply a data detection algorithm to a detector input derived from the data input to yield a detected output; and

a data decoder circuit operable to apply a data decoding algorithm to the detected output to yield a decoded data set.

15. The device of claim 14 , wherein the inter-track interference mitigation circuit comprises:

a filter circuit operable to filter a data set derived from a track adjacent to the target track to yield inter-track interference values corresponding to the analog input; and

a summation circuit operable to subtract the inter-track interference values from the sample set to yield the corrected series of samples.

16. A data processing system, the system comprising:

an analog to digital converter circuit operable to convert an analog input into a series of digital samples;

an inter-track interference mitigation circuit including:

a filter circuit operable to filter a data set derived from a track adjacent to the track from which the analog input is derived to yield inter-track interference values corresponding to the analog input; and

a summation circuit operable to subtract the inter-track interference values from the series of digital samples to yield a corrected series of samples; and

an equalizer circuit operable to apply an equalization algorithm to the corrected series of samples to yield an equalized output.

17. The system of claim 16 , wherein the filter circuit is a digital finite impulse response circuit governed by a plurality of filter taps.

18. The system of claim 16 , wherein the data set derived from the track adjacent to the track from which the analog input is derived is selected from a group consisting of: an x-sample data set, and a y-sample data set.

19. The system of claim 16 , wherein the data set derived from the track adjacent to the track from which the analog input is derived is generated by re-reading the track adjacent to the track from which the analog input is derived.

20. The system of claim 16 , wherein the data set derived from the track adjacent to the track from which the analog input is derived is generated by buffering data generated during prior processing of the data set derived from the track adjacent to the track from which the analog input is derived.

21. The system of claim 16 , the system further comprising:

a data processing circuit operable to apply a combination of a data detection algorithm and a data decoding algorithm to the equalized output to yield an originally written data set.