Image sensor

1. An image sensor, comprising:

a semiconductor substrate having an active array region and a peripheral circuit region thereon;

a plurality of photosensor elements in the active array region of the semiconductor substrate;

a first dielectric layer on the semiconductor substrate covering the active array region and the peripheral circuit region; and

a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a recess region corresponding the active array region, the recess region exposes a top surface of the first dielectric layer, wherein a perimeter of the recess region is defined by a sidewall of the second dielectric layer, and wherein an angle between the sidewall of the second dielectric layer and the top surface of the first dielectric layer is less than 90 degrees.

2. The image sensor according to claim 1 , wherein the first dielectric layer is a silicon oxide layer.

3. The image sensor according to claim 1 , wherein the second dielectric layer is a silicon oxide layer.

4. The image sensor according to claim 1 further comprising a first metal interconnection layer on the semiconductor substrate, and the first dielectric layer covers the first metal interconnection layer.

5. The image sensor according to claim 4 further comprising a second metal interconnection layer on the first dielectric layer, and the second dielectric layer covers the second metal interconnection layer.

6. The image sensor according to claim 5 , wherein the first metal interconnection layer and the second metal interconnection layer are disposed within the peripheral circuit region.

7. A method for fabricating an image sensor, comprising:

providing a semiconductor substrate having an active array region and a peripheral circuit region thereon, wherein a plurality of photosensor elements is disposed in the active array region;

forming a first dielectric layer on the semiconductor substrate to cover the active array region and the peripheral circuit region;

forming a sacrificial layer pattern on the first dielectric layer within the active array region, wherein an angle between a sidewall of the sacrificial layer pattern and a top surface of the first dielectric layer is greater than 90 degrees;

forming a second dielectric layer on the first dielectric layer not covered by the sacrificial layer pattern; and

removing the sacrificial layer pattern to expose a portion of the first dielectric layer.

8. The method according to claim 7 , wherein said forming a sacrificial layer pattern further comprises:

forming a sacrificial layer on the first dielectric layer;

forming a photoresist pattern on the sacrificial layer; and

performing an etching process to remove a portion of the sacrificial layer not covered by the photoresist pattern.

9. The method according to claim 7 , wherein the sacrificial layer pattern comprises silicon oxynitride, amorphous carbon, or photosensitive polymeric materials.

10. The method according to claim 7 , wherein said forming a second dielectric layer further comprises an atomic layer deposition (ALD) process or a low-temperature CVD process.

11. The method according to claim 7 , wherein after forming the second dielectric layer, a portion of the second dielectric layer directly above the sacrificial layer pattern is removed by using a planarization process.

12. The method according to claim 7 , wherein after removing the sacrificial layer pattern, the method further comprises forming a color filter film and a micro-lens structure on the exposed portion of the first dielectric layer.