Thin film transistor array panel and liquid crystal display device including the same

1. A thin film transistor array panel, comprising:

a first substrate;

a gate line lengthwise extended in a first direction and a data line lengthwise extended in a second direction intersecting with the first direction, on the first substrate;

a storage electrode line on the first substrate, wherein a constant voltage is applied thereto;

a first thin film transistor which is connected to the gate line and the data line, and comprises a first gate electrode, a first source electrode and a first drain electrode;

a second thin film transistor which is connected to the gate line and the data line, and comprises a second gate electrode, a second source electrode and a second drain electrode;

a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line, and comprises a third gate electrode, a third source electrode and a third drain electrode;

a first subpixel electrode which is connected to the first thin film transistor; and

a second subpixel electrode which is connected to the second thin film transistor,

wherein

the first, second and third gate electrodes are defined extended in the second direction from a same gate line to overlap the first, second and third drain electrodes, respectively,

the second and third thin film transistors are spaced apart from each other in the first direction in which the gate line is lengthwise extended,

the third source electrode of the third thin film transistor is directly connected to the second drain electrode of the second thin film transistor, and

the second drain electrode and third source electrode directly connected to each other define lengthwise extensions thereof in the first direction in which the second and third thin film transistors are spaced apart from each other, the lengthwise extension in the first direction overlapping the second gate electrode of the second thin film transistor and the third gate electrode of the third thin film transistor which is spaced apart from the second thin film transistor in the first direction, respectively.

2. The thin film transistor array panel of claim 1 , wherein:

the third gate electrode defines an extension electrode thereof which extends to overlap the first drain electrode.

3. The thin film transistor array panel of claim 2 , wherein

the first and third thin film transistors are spaced apart from each other in the first direction in which the gate line is lengthwise extended, and

the extension electrode defines a lengthwise extension thereof in the first direction in which the first and third thin film transistors are spaced apart from each other, the extension of the third gate electrode overlapping the first drain electrode of the first thin film transistor which is spaced apart from the third thin film transistor.

4. The thin film transistor array panel of claim 3 , wherein the extension electrode is spaced apart from the first gate electrode.

5. The thin film transistor array panel of claim 4 , wherein:

the first drain electrode includes:

a first portion which has a rod shape, is enclosed by the first source electrode and overlaps the first gate electrode;

a second portion which is connected to the first portion, is wider than the first portion and is between the first gate electrode and the extension electrode; and

a third portion which is connected to the second portion, has a rod shape, is narrower than the second portion and overlaps the extension electrode.

6. The thin film transistor array panel of claim 1 , further comprising:

an auxiliary electrode which protrudes from the storage electrode line;

wherein

the first gate electrode and the second gate electrode are connected to each other,

the first source electrode protrudes from the data line and overlaps the first gate electrode, and the first drain electrode is spaced apart from the first source electrode,

the second source electrode is connected to the first source electrode and overlaps the second gate electrode, and the second drain electrode includes the drain electrode of the second thin film transistor which is spaced apart from the second source electrode,

the third gate electrode is spaced apart from the second gate electrode in the first direction,

the third source electrode includes the source electrode of the third thin film transistor which is connected to the second drain electrode and overlaps the third gate electrode, and

the third drain electrode is spaced apart from the third source electrode and overlaps the third gate electrode and the auxiliary electrode.

7. The thin film transistor array panel of claim 6 , further comprising:

a connection electrode which connects the third drain electrode and the auxiliary electrode to each other.

8. The thin film transistor array panel of claim 6 , wherein:

the second drain electrode and the third source electrode are between the second gate electrode and the third gate electrode which are spaced apart from each other.

9. The thin film transistor array panel of claim 8 , wherein:

the first source electrode and the second source electrode are curved in a ‘C’ shape.

10. The thin film transistor array panel of claim 9 , wherein:

the first drain electrode and the second drain electrode each include:

a first portion having a rod shape; and

a second portion which is connected to the first portion and is wider than the first portion,

the first portion of first drain electrode is enclosed by the first source electrode,

the first portion of the second drain electrode is enclosed by the second source electrode, and

the first portion of the second drain electrode is connected to the third source electrode via the second portion of the second drain electrode.

11. The thin film transistor array panel of claim 10 , further comprising:

a gate insulating layer on the gate line, the first gate electrode, the second gate electrode and the third gate electrode; and

a passivation layer on the first, second and third source electrodes and on the first, second and third drain electrodes.

12. The thin film transistor array panel of claim 11 , wherein

the passivation layer comprises:

a first contact hole which exposes a portion of the first drain electrode; and

a second contact hole which exposes a portion of the second drain electrode; and

the passivation layer and the gate insulating layer comprise a third contact hole which exposes a portion of the third drain electrode and a portion of the auxiliary electrode.

13. The thin film transistor array panel of claim 12 , further comprising:

a connection electrode which is connected to the third drain electrode and the auxiliary electrode through the third contact hole,

wherein

the first subpixel electrode is connected to the first drain electrode through the first contact hole, and

the second subpixel electrode is connected to the second drain electrode through the second contact hole.

14. The thin film transistor array panel of claim 13 , wherein:

the portion of the auxiliary electrode exposed by the third contact hole does not overlap the third drain electrode.

15. The thin film transistor array panel of claim 13 , wherein:

the connection electrode includes a same material, and is in a same layer as the first subpixel electrode and the second subpixel electrode.