IP Library Granted Patent US 9,983,794
Granted Patent B2
US 9,983,794 · App. 14/700,625 · Granted May 29, 2018

Memory device and host device

Inventor: Akihisa Fujimoto (Yamoto, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0608G06F3/0658G06F3/0679
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Quick Facts
Patent No.
US 9,983,794
App. No.
14/700,625
Granted
May 29, 2018
Kind
B2
Abstract

According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

Claims (19)

1. A memory device comprising:

a nonvolatile semiconductor memory having a plurality of physical storage areas that include a user area externally accessible, the user area being divided into plurality of allocation units; and

a control unit configured to control the nonvolatile semiconductor memory, wherein

the control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns an allocation unit of the plurality of allocation units represented by an address of the read command or the write command as the sequential write area, and changes memory access control when an address of a memory access command to access the user area indicates no access in the sequential write area whose size is equivalent to the allocation unit, and

an allocation unit of the plurality of allocation units is divided into plurality of recording units, when the address of the write command for the sequential write area is an address not to cause overwrite, the data length of the write command is equivalent to one or plurality of recording unit and a data location is on a recording unit boundary, the memory access control controls a busy time to make average write performance higher than a performance index (Pw), and if the condition is not met, the memory access control can indicate a busy time that does not meet the performance index.

2. The memory device according to claim 1 , wherein the control unit sets an area in the allocation unit from an address position of the read command or a position next to data written by the write command to an end of the allocation unit as an area in which next data can be written, and if data stored in an area before the address designated by the read command or the write command exists, preserves the data.

3. The memory device according to claim 1 , further comprising a register configured to hold a performance index which indicates minimum average write performance to the sequential write area and a size of an allocation unit of the plurality of allocation units, wherein the register can externally be read out.

4. The memory device according to claim 1 , wherein the control unit receives a control command having a second argument to designate an overwrite area and the read command or the write command, assigns an allocation unit of the plurality of allocation units whose start position is represented by the address of the read command or the write command as the overwrite area, and changes the memory access control by judging concerning the memory access command to access the user area whether the address of the memory access command indicates access in the overwrite area.

5. The memory device according to claim 4 , wherein a size of the overwrite area is determined by one of a third argument of the control command, or a size of a data area accessed by the read command or the write command.

6. The memory device according to claim 4 , wherein the control unit sets a maximum busy time at the time of write in an unassigned area longer than the maximum busy time at the time of write in the designated overwrite area or sequential write area, and performs the memory access control to indicate different busy times so that an average busy time at the time of write in the unassigned area can be made longer than the average busy time at the time of write in the designated overwrite area or sequential write area.

7. The memory device according to claim 6 , wherein when a power supply of the memory device is maintained, assignment information of the designated sequential write area and overwrite area is held.

8. The memory device according to claim 7 , wherein a plurality of overwrite areas in number not more than a predetermined value can be assigned, and if the overwrite areas in number more than the predetermined value are designated, latest overwrite areas in number equal to the predetermined value are assigned as the overwrite areas.

9. The memory device according to claim 4 , wherein the control unit receives a control command having a fourth argument to designate a data area of a file system and the read command whose address indicates a start address of the data area of the file system, and assigns the user area as a overwrite area based on the address of the read command.

10. The memory device according to claim 4 , wherein

the control command has a fifth argument to designate the sequential write area first, and

the control unit processes the control command having the fifth argument as the control command having the first argument.

11. The memory device according to claim 10 , wherein when write of the write command indicates the data length is equivalent to one or plurality of recording unit and the data location is on the recording unit boundary, a write destination indicates write up to an end of the assigned sequential write area, and a next write command indicates write to be performed from a start of another allocation unit and the data length of the write command is equivalent to one or plurality of recording unit and the data location is on the recording unit boundary, the control unit assigns the newly written user area as the sequential write area.

12. The memory device according to claim 10 , wherein upon receiving the control command indicating a position of a directory entry of a file system, the control unit determines a start position of the overwrite area by an address of the write command following the control command, assigns an area in a size including an area to be written by the write command as the overwrite area, and if the area has already been assigned as the overwrite area, maintains the assignment.

13. The memory device according to claim 10 , wherein upon receiving the control command indicating a position to write a part of small data other than stream data during recording of the stream data, the control unit determines a start position of the overwrite area by an address of the write command following the control command, assigns an area in a size including an area to be written by the write command as the overwrite area, and if the area has already been assigned as the overwrite area, maintains the assignment.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2015
From: FUJIMOTO, AKIHISA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 035538/0924 →
Priority Claims (2)
JP 2012-238849 · Oct 30, 2012 · national
JP 2013-166804 · Aug 9, 2013 · national
Continuity (2)
Continuation PCTJP2013074959 · Sep 10, 2013
Related Publication 20150234598A1 · Aug 20, 2015