System for accelerated network route update through exclusive access to routing tables
View Patent ↗A route update system (RUS) may support increased efficiency and speed for performing a routing table update. The RUS may include a control plane processor device, which may implement update snoop module circuitry. The RUS may also include a data routing switch, which may implement update inject module circuitry. The RUS may include one or more RUS connectivity systems that link the update snoop module circuitry and the update inject module circuitry.
1. A device comprising:
search logic circuitry configured to receive network data packets and provide a route search request to a routing table memory, the network data packets being addressed to another device;
update injection module circuitry configured to receive and unpack a hard application program interface (hardAPI) packet comprising a plurality of route update instructions, the hardAPI packet being addressed to the device; and
table memory arbiter circuitry configured to
arbitrate between at least the search logic circuitry and the update injection module circuitry to selectively allow either the route search request, or the plurality of route update instructions, exclusive access to a routing table memory of the device, and
provide a first flow control signal to reduce a number of memory access requests received from the search logic circuitry to allow the route update instructions to complete update of the routing table memory.
2. The device of claim 1 , wherein the update injection module is further configured to authenticate a source and destination of the hardAPI packet based on a source address and a destination address included in the hardAPI packet, the source address being an internett protocol (IP) address and/or a media access control (MAC) address of the source, and the destination address being an IP address and/or a MAC address of the device.
3. The device of claim 1 , wherein the hardAPI packet includes an indication that a group of memory locations in the routing table memory are to be updated with atomicity by at least one of the plurality of route update instructions, and the table memory arbiter circuitry is configured to maintain access to the routing table memory for a period of time that allows the group of memory locations in the routing table memory to be updated without interruption.
4. The device of claim 1 , wherein the hardAPI packet includes a header and a payload limited to Open System Interconnect layer three or below, and the payload is directly readable by the update injection module circuitry.
5. The device of claim 1 , wherein the update injection module circuitry is further configured to generate a second flow control signal that is transmitted for receipt by a source of the hardAPI packet.
6. The device of claim 1 , wherein the table memory arbiter is included in the update injection module circuitry.
7. The device of claim 1 , wherein the update injection module circuitry is further configured to authenticate a signature included in the hardAPI packet, and perform formatting of the hardAPI packet in response to successful authentication of the signature.
8. The device of claim 1 , wherein the update injection module circuitry is further configured to capture and store summary information regarding the route update instructions, in connection with a current time stamp, wherein the stored summary information and current time stamp are used to recover a recently updated version of the routing table stored in the routing table memory.
9. The device of claim 1 , further comprising a central processing unit (CPU) configured to receive a soft application program interface (softAPI) packet addressed to the device, the CPU further configured to process the softAPI packet and generate route update instructions, the table memory arbiter circuitry configured to arbitrate between the search logic circuitry, the update injection module circuitry, and the CPU to selectively allow access to the routing table memory of the device by only one of the route search request, or the plurality of route update instructions of the update injection module circuitry, or the route update instructions of the CPU.
10. A method of updating a routing table comprising:
receiving a network data packet with search logic circuitry, and creating a route search request to search in a routing table memory;
receiving a hard application program interface (hardAPI) packet with update injection module circuitry and extracting a route update instruction from the hardAPI packet, the hardAPI packet including a payload limited to Open System Interconnect layer three and below, and the route update instruction being to update the routing table memory;
arbitrating, with table memory arbiter circuitry, between allowing exclusive access to the routing table in the memory by either the route search request, or the route update instruction; and
providing, by the table memory arbiter circuit, a first flow control signal to reduce a number of memory access requests received from the search logic circuitry to allow the route update instruction to complete update of the routing table memory.
11. The method of claim 10 , further comprising updating with atomicity a group of memory locations in the routing table memory using the route update instruction by blocking access to the routing table memory by the search logic circuitry.
12. The method of claim 10 , further comprising the update injection module circuitry authenticating a source of the hardAPI packet and unpacking a plurality of route update instructions included in the hardAPI packet.
13. The method of claim 10 , further comprising identifying presence of encryption in the hardAPI packet and decrypting the payload based on a locally stored key before extracting the route update instruction from the payload.
14. An apparatus comprising:
circuitry configured to
receive network data packets addressed to another apparatus;
receive and unpack a hard application program interface (hardAPI) packet addressed to the apparatus, the hardAPI comprising a plurality of route update instructions; and
selectively allow either the route search request, or the plurality of route update instructions, exclusive access to a routing table memory of the apparatus, and
provide a first flow control signal to reduce a number of route search requests received from the search logic circuitry to allow the route update instructions to complete update of the routing table memory.
15. The apparatus of claim 14 , wherein the circuitry is configured to authenticate a source and destination of the hardAPI packet based on a source address and a destination address included in the hardAPI packet, the source address being an internet protocol (IP) address and/or a media access control (MAC) address of the source, and the destination address being an IP address and/or a MAC address of the apparatus.
16. The apparatus of claim 14 , wherein the hardAPI packet includes an indication that a group of memory locations in the routing table memory are to be updated with atomicity by at least one of the plurality of route update instructions, and the circuitry is configured to maintain access to the routing table memory for a period of time that allows the group of memory locations in the routing table memory to be updated without interruption.
17. The apparatus of claim 14 , wherein the hardAPI packet includes a header and a payload limited to Open System Interconnect layer three or below, and the payload is directly readable by the circuitry.
18. The apparatus of claim 14 , wherein circuitry is configured to:
authenticate a signature included in the hardAPI packet; and
perform formatting of the hardAPI packet in response to successful authentication of the signature.
19. The apparatus of claim 14 , wherein the circuitry is configured to capture and store summary information regarding the route update instructions, in connection with a current time stamp, wherein the stored summary information and current time stamp are used to recover a recently updated version of the routing table stored in the routing table memory.
20. The apparatus of claim 14 , wherein the circuitry is configured to:
receive a soft application program interface (softAPI) packet addressed to the apparatus;
process the softAPI packet and generate route update instructions; and
selectively allow access to the routing table memory of the apparatus by only one of the route search request, or the plurality of route update instructions included in the hardAPI, or the route update instructions generated from the softAPI.