Executing an instruction of currently active thread before context switch upon receiving inactive context ID to be activated
View Patent ↗Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
1. A method for context switching in an electronic processor, comprising:
receiving, at the electronic processor from a scheduler, an identity of a first context, the first context currently inactive;
performing, at the electronic processor after the receiving the identity of the first context, a first instruction of a thread associated with a second context, the second context currently active;
storing, at the electronic processor at a context program counter register of the second context, a program counter of the first instruction; and
pointing, at the electronic processor, a processor program counter to a context program counter register of the first context.
2. The method of claim 1 , further comprising:
setting, at the electronic processor, a bit of a context status register of the second context, the bit indicating that the second context is awaiting data from an external device.
3. The method of claim 2 , wherein the setting is performed before the receiving.
4. The method of claim 2 , further comprising clearing the bit of the context status register of the second context after the second context has received the data from the external device.
5. The method of claim 2 , further comprising storing an identity of a register, the identity of the register stored at a field of a second instruction of the thread, the register configured to store the data from the external device.
6. The method of claim 5 , wherein the second instruction is performed before the first instruction.
7. A system for context switching, comprising:
a memory configured to store an identity of a first context, the first context currently inactive; and
an electronic processor having a context program counter register of the first context, a context program counter register of a second context, and a processor program counter, the electronic processor configured to perform, after the identity of the first context is stored in the memory, a first instruction of a thread associated with the second context, the second context currently active, the electronic processor configured to store, at the context program counter register of the second context, a program counter of the first instruction, and the electronic processor configured to point the processor program counter to the context program counter register of the first context.
8. The system of claim 7 , wherein the electronic processor has a context status register of the second context, the electronic processor further configured to set a bit of the context status register of the second context, the bit indicating that the second context is awaiting data from an external device.
9. The system of claim 8 , wherein the electronic processor is configured to set the bit of the context status register of the second context before the identity of the first context is stored in the memory.
10. The system of claim 8 , wherein the electronic processor is configured to clear the bit of the context status register of the second context after the second context has received the data from the external device.
11. The system of claim 8 , wherein the electronic processor has a write address register of the second context, the electronic processor further configured to store, in the write address register of the second context, an identity of a register, the identity of the register stored in a field of a second instruction of the thread, the register configured to store the data from the external device.
12. The system of claim 11 , wherein the electronic processor is configured to perform the second instruction before the first instruction.