Noise mitigation for write precompensation tuning

1. A method comprising:

writing a predetermined pattern at different radial offsets from a target data track in a data storage device; and

identifying a radial offset where a data write of the predetermined pattern provides substantially highest mitigation of fluctuation in a bit error rate for subsequent data reads of the target data track.

2. The method of claim 1 , wherein the predetermined pattern is a single-bit transition pattern.

3. The method of claim 1 , further comprising:

cleaning the target data track by writing the predetermined pattern at an offset corresponding to the identified radial offset on both sides of the target data track;

testing a write precompensation register in association with the target data track after the cleaning of the target data track.

4. The method of claim 3 , wherein testing the write precompensation register further comprises:

writing a random pattern along the cleaned target data track and along a data track directly adjacent to the cleaned target data track according to one or more timing delays specified by the write precompensation register;

reading the random pattern from the cleaned target data track; and

determining a bit error rate of the read operation.

5. The method of claim 1 , wherein writing the predetermined data pattern at each of the different radial offsets further comprises:

writing the predetermined data pattern at a select one of the radial offsets;

writing a random pattern along the target data track;

writing a random pattern along a data track directly adjacent to the target data track;

reading the random pattern from the target data track; and

measuring a bit error rate of the read operation.

6. The method of claim 1 , wherein a storage medium of the storage device is a shingled magnetic storage medium.

7. A system comprising:

at least one processor;

a memory; and

an offset determination engine stored in the memory and executable by the at least one processor, the offset determination engine configured to write a predetermined pattern at different radial offsets from a target data track on a storage medium to identify a radial offset where a data write of the predetermined pattern provides substantially highest mitigation of fluctuation in a bit error rate for subsequent data reads of the target data track.

8. The system of claim 7 , further comprising:

a track clean-up engine stored in the memory and executable by the at least one processor, the track clean-up engine configured to clean the target data track by writing the predetermined pattern at an offset corresponding to the identified radial offset.

9. The system of claim 8 , further comprising:

a write precompensation register selector stored in memory and executable by the at least one processor, the write precompensation register selector configured to test a write precompensation register in association with the cleaned target data track storing the predefined pattern at the identified radial offset.

10. The system of claim 8 , wherein the track clean-up engine writes the predetermined pattern at the identified radial offset following each test of a different write precompensation register.

11. The system of claim 9 , wherein the write precompensation register selector saves, in a storage device memory, a substantially optimal write precompensation register in association with a radial zone including the target data track.

12. The system of claim 9 , wherein the write precompensation register selector is configured to test the write precompensation register by:

writing a random pattern along the cleaned target data track and along a data track directly adjacent to the target data track according to at least one timing delay specified by the write precompensation register;

reading the random pattern from the target data track; and

determining a bit error rate of the read data.

13. The system of claim 7 , wherein the predetermined pattern is a single-bit transition pattern.

14. The system of claim 7 , wherein the offset determination engine is configured to write the predetermined pattern at each of the different radial offsets by:

writing the predetermined data pattern at a select one of the radial offsets;

writing a random pattern along the target data track;

writing a random pattern along a data track directly adjacent to the target data track;

reading the random pattern from the target data track; and

measuring a bit error rate of the read operation.

15. The system of claim 7 , wherein the storage medium is a shingled magnetic storage medium.

16. A method comprising:

writing a predetermined pattern at a number of radial offsets from a target data track in a data storage device;

selecting one of the radial offsets; and

writing the predetermined pattern at the selected radial offset before testing accuracy of a write precompensation register for use in association with the target data track.

17. The method of claim 16 , wherein a bit error rate fluctuation for data reads of the target data track is mitigated when the predetermined pattern is written at the selected radial offset prior to each data write to the target data track.

18. The method of claim 16 , wherein the predetermined pattern is a single bit transition pattern.

19. The method of claim 16 , wherein the selecting of one of the radial offsets further comprises:

writing a predetermined pattern at a one of the radial offsets from the target data track;

writing a random pattern along the target data track;

writing a random pattern along a data track directly adjacent to the target data track;

reading the random pattern from the target data track; and

determining a bit error rate of the read data.

20. The method of claim 16 , wherein the data storage device is a shingled magnetic recording device.