Integrated circuit arrangement
View Patent ↗An integrated circuit arrangement includes a flange, a transistor die, and a first conducting element defining a lead. The flange includes a conducting material and the transistor die is disposed on a surface of the flange. The first conducting element is electrically connected to the transistor die via connecting elements to allow current flow from the transistor die. The flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die. The flange includes one or more reduced thickness portions that are configured to limit the return current paths and control current flow passing through the flange to the transistor die.
1. An integrated circuit arrangement comprising:
a flange, the flange comprising conducting material;
a transistor die disposed on a surface of the flange;
an elongate capacitor bar disposed on the surface of the flange;
a first conducting element defining a lead, the first conducting element being electrically connected to the transistor die via connecting elements to allow current flow from the transistor die;
wherein the flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die, wherein the flange comprises one or more reduced thickness portions, the one or more reduced thickness portions being configured to limit the return current paths and therewith to control current flow passing through the flange to the transistor die, wherein the one or more reduced thickness portions correspond to one or more pits in the flange surface, wherein the one or more pits comprise an elongate trench, wherein a longitudinal axis of the elongate trench is parallel to a longitudinal axis of the transistor die, wherein the elongate trench is located between at least one of: i) the elongate capacitor bar and the first conducting element or ii) the elongate capacitor bar and the transistor die.
2. The integrated circuit arrangement of claim 1 , wherein the one or more pits have a depth of between 100 and 500 microns.
3. The integrated circuit arrangement of claim 1 , wherein the transistor die comprises an elongate transistor bar, and wherein the elongate trench is arranged side by side with the elongate transistor bar.
4. The integrated circuit arrangement of claim 1 , wherein the elongate capacitor bar is arranged between the transistor die and the first conducting element, and wherein the elongate trench is located between the elongate capacitor bar and the first conducting element.
5. The integrated circuit arrangement of claim 1 , wherein the elongate capacitor bar is arranged between the transistor die and the first output terminal, and wherein the elongate trench is located between the elongate capacitor bar and the transistor die.
6. The integrated circuit arrangement of claim 1 , wherein the integrated circuit arrangement comprises a second conducting element in the form of a lead configured to provide for an electrical connection, via connecting elements between the die and an input terminal.
7. The integrated circuit arrangement of claim 1 , wherein the integrated circuit arrangement comprises two or more elongate transistor dies.
8. The integrated circuit arrangement of claim 7 , wherein the two or more elongate transistor dies are arranged end to end on the surface of the flange, in a parallel configuration.
9. The integrated circuit arrangement of claim 1 , wherein the integrated circuit arrangement comprises an Over Molded plastic packaging.
10. The integrated circuit arrangement of claim 1 , wherein the transistor die comprises a MOSFET or a LDMOS-based transistor.
11. The integrated circuit arrangement of claim 1 , wherein the transistor die is an integrated amplifier die.
12. The integrated circuit arrangement of claim 1 , wherein the integrated circuit arrangement comprises a power amplifier.
13. The integrated circuit arrangement of claim 12 , wherein the power amplifier is a radio-frequency (RF) power amplifier.
14. The integrated circuit arrangement of claim 1 , wherein the integrated circuit arrangement comprises at least one of a Doherty amplifier and a push-pull amplifier.
15. The integrated circuit arrangement of claim 1 , wherein a longitudinal axis of the elongate trench is parallel to a longitudinal axis of the transistor die embodied as a transistor bar.
16. The integrated circuit arrangement of claim 1 , wherein the reduced thickness portion has a thickness of between 50% and 95% of the thickness of the bulk of the flange.
17. The integrated circuit arrangement of claim 1 , wherein the reduced thickness portion extends into a top surface of the flange.
18. The integrated circuit arrangement of claim 1 , wherein a position of the one or more reduced thickness portions is based on a desired uniformity of impedance along a length of the transistor die.