Cortical processing with thermodynamic RAM
View Patent ↗A thermodynamic RAM apparatus includes a physical substrate of addressable adaptive synapses that are temporarily partitioned to emulate adaptive neurons of arbitrary sizes, wherein the physical substrate mates electronically with a digital computing platform for high-throughput and low-power neuromorphic adaptive learning applications. The physical substrate addressable adaptive synapses can be configured as a part of a memristor-based physical neural processing unit.
1. A thermodynamic RAM apparatus, comprising:
a collection of thermodynamic cores; and
a plurality of common read out electrodes, wherein each thermodynamic core among said collection of thermodynamic cores comprises a physical substrate of individually addressable adaptive synapses that are selectively coupled to said plurality of common read-out electrodes, and wherein said physical substrate provides a synaptic integration and a learning resource for digital computing platforms.
2. The thermodynamic RAM apparatus of claim 1 wherein said individually addressable adaptive synapses comprise memsistors.
3. The thermodynamic RAM apparatus of claim 1 wherein said individually addressable adaptive synapses comprise transistors.
4. The thermodynamic RAM apparatus of claim 1 wherein said each thermodynamic core is emulated with digital electronics.
5. A method for synaptic integration and learning with thermodynamic RAM, said method comprising:
coupling individual synaptic elements to common driving electrodes; and
executing at least one instruction via an AHaH (Anti-Hebbian and Hebbian) controller to drive said common driving electrodes.
6. A thermodynamic RAM apparatus, comprising
physical substrate of addressable adaptive synapses that are partitioned to emulate adaptive neurons of arbitrary sizes, wherein said physical substrate mates electronically with a digital computing platform for neuromorphic adaptive learning applications.
7. The thermodynamic RAM apparatus of claim 6 wherein said physical substrate addressable adaptive synapses are configured as a part of a memristor-based physical neural processing unit.
8. The apparatus of claim 2 wherein at least one thermodynamic core among said plurality of thermodynamic cores comprises a nibble core that treats said memristors as having at most 16 discrete states and which stores a synapse with at most one byte.
9. The apparatus of claim 2 wherein at least one thermodynamic core among said plurality of thermodynamic cores comprises a byte core that treats said memristors as having at most 256 discrete states and which stores a synapse with at most two bytes.
10. The apparatus of claim 2 wherein at least one thermodynamic core among said plurality of thermodynamic cores comprises a float core that treats said memristors as having a floating-point representation and which stores a synapse with two floating point numbers.
11. The apparatus of claim 2 wherein at least one thermodynamic core among said plurality of thermodynamic cores comprises:
a nibble core that treats each memristor among said memristors as having discrete states and wherein each nibble core stores a synapse with at most one byte;
a byte core that treats said memristors as having at most 256 discrete states and which stores a synapse with at most two bytes; and
a float core treats said memristors as a floating point number and which stores a synapse with at most two floating point numbers.