Devices having multiple threshold voltages and method of fabricating such devices
View Patent ↗Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.
1. A method of fabricating devices on a semiconductor substrate, the method comprising:
providing a first fixed charge region to the semiconductor substrate below an interface between an insulating layer above the semiconductor substrate and the semiconductor substrate for a first device of the devices, the first fixed charge region having a first configuration; and
providing a second fixed charge region to the semiconductor substrate below the interface between the insulating layer above the semiconductor substrate and the semiconductor substrate for a second device of the devices, the second fixed charge region having a second configuration, the first configuration being different than the second configuration.
2. The method of claim 1 , wherein the devices are FDSOI device, wherein the insulating layer is a buried oxide (BOX) layer, and wherein each of the first configuration and the second configuration comprises an electrical polarity and a concentration of charges.
3. The method of claim 1 , wherein the first device has an ultra-high threshold voltage (UHVT) level, the first device being a fully depleted silicon-on-insulator (FDSOI) N-type metal oxide semiconductor (NMOS) device, the semiconductor substrate at a location associated with the first device being P-type, the first fixed charge region comprising negative fixed charges.
4. The method of claim 1 , wherein the first device has a high threshold voltage (HVT) level, the first device being a FDSOI NMOS device, the semiconductor substrate at a location associated with the first device being N-type, the first fixed charge region comprising negative fixed charges.
5. The method of claim 1 , wherein the first device has a low threshold voltage (LVT) level, the first FDSOI device being a FDSOI NMOS device, the semiconductor substrate at a location associated with the first device being P-type, the first fixed charge region comprising positive fixed charges.
6. The method of claim 1 , wherein the first device has a ultra-low threshold voltage (ULVT) level, the first FDSOI device being a FDSOI NMOS device, the semiconductor substrate at a location associated with the first device being N-type, the first fixed charge region comprising positive charges.
7. The method of claim 1 , wherein the second device has a ultra-high threshold voltage (UHVT) level, the second device being a FDSOI P-type metal oxide semiconductor (PMOS) device, the semiconductor substrate at a location associated with the second device being N-type, the second fixed charge region comprising positive charges.
8. The method of claim 1 , wherein the second device has a high threshold voltage (HVT) level, the second device being a FDSOI PMOS device, the semiconductor substrate at a location associated with the second device being P-type, the second fixed charge region comprising positive charges.
9. The method of claim 1 , wherein the second device has a low threshold voltage (LVT) level, the second device being a FDSOI PMOS device, the semiconductor substrate at a location associated with the second device being N-type, the second fixed charge region comprising negative charges.
10. The method of claim 1 , wherein the second device has a ultra-low threshold voltage (ULVT) level, the second device being a FDSOI PMOS device, the semiconductor substrate at a location associated with the second device being P-type, the second fixed charge region comprising negative charges.
11. A silicon on insulator (SOI) circuit, the SOI circuit comprising:
a doped semiconductor substrate;
a buried insulating layer disposed above the doped semiconductor substrate;
a silicon film disposed above the buried insulating layer;
a first region comprising first fixed charges disposed in the doped semiconductor substrate proximate to an interface between the doped semiconductor substrate and the buried insulating layer; and
a second region comprising second fixed charges disposed in the doped semiconductor substrate proximate to the interface between the doped semiconductor substrate and the buried insulating layer, the first region having a first configuration, the second region having a second configuration, the first configuration being different than the second configuration.
12. The SOI circuit of claim 11 , further comprising a gate disposed above the silicon film, the SOI circuit comprising a device, the device being a fully depleted device, the buried insulating layer being a buried oxide layer.
13. The SOI circuit of claim 11 , wherein the fixed charges are negative fixed charges introduced by halogen dopants.
14. The SOI circuit, of claim 11 , wherein the fixed charges are positive fixed charges introduced by nitrogen group dopants.
15. The SOI circuit of claim 13 , wherein the halogen dopants are fluorine (F).
16. The SOI circuit of claim 14 , wherein the nitrogen group dopants are nitrogen (N).
17. A method of fabricating devices on a silicon on an insulator (SOI) substrate, wherein the SOI substrate comprises a semiconductor substrate, an insulating layer disposed above the semiconductor substrate, and a silicon film disposed above the insulating layer, the method comprising:
implanting first dopants to the semiconductor substrate for a first device of the devices;
implanting second dopants to a first region proximate to an interface between the insulating layer and the semiconductor substrate for the first device, wherein the second dopants form a first fixed charge region;
implanting third dopants to the semiconductor substrate for a second device of the devices; and
implanting fourth dopants to a second region proximate to an interface between the insulating layer and the semiconductor substrate for the second device, wherein the fourth dopants form a second fixed charge region.
18. The method of claim 17 , wherein the first dopants comprise n-type dopants or p-type dopants, and wherein the third dopants comprises p-type dopants or n-type dopants.
19. The method of claim 18 , wherein the second dopants comprise fluorine, wherein the fourth dopants comprise nitrogen, and wherein the devices comprise fully depleted silicon-on-insulator (FDSOI) devices.
20. The method of claim 18 , wherein the second dopants comprise nitrogen, wherein the fourth dopants comprise fluorine, and wherein the devices comprise fully depleted silicon-on-insulator (FDSOI) devices.