IP Library Granted Patent US 9,715,590
Granted Patent B2
US 9,715,590 · App. 14/704,947 · Granted Jul 25, 2017

System and device for verifying the integrity of a system from its subcomponents

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Quick Facts
Patent No.
US 9,715,590
App. No.
14/704,947
Granted
Jul 25, 2017
Kind
B2
Abstract

A system and device for verifying the integrity of a system from its subcomponents, the system comprising a plurality of subcomponents each having a physical state, the system and the device comprising a processor that is connected to each of the subcomponents, the processor configured to verify systemic integrity by performing verification on some or all specified subcomponents. The verification may be individual (1,1) or threshold (n,1), and may be interactive or non-interactive.

Claims (26)

1. A system of components configured to attest integrity of the system, the components having a physical state and comprising:

a) a physical unclonable function (‘PUF’) including a PUF input and a PUF output and constructed to generate, in response to the input of a specific challenge, an output value that is characteristic to i) the PUF, ii) the component's physical state, and iii) the specific challenge; and

b) a processor connected to the PUF and configured to, in response to a verification request, provide an input to the PUF input and receive a response from the PUF output, and compute a share for a respective PUF-containing component of a joint threshold proof.

2. The device of claim 1 , wherein a respective processor is further configured to convey the share it computes to a secretary.

3. The device of claim 1 , wherein the system of components is arranged in a ring and one or more of the processors is configured to convey the share it computes to another component in the ring.

4. The device of claim 1 , wherein the joint threshold proof is a zero knowledge proof.

5. A computing system having a high-assurance processor that provides the computing system a hardware root-of-trust, the computing system comprising:

a high-assurance processor that includes a physical unclonable function (‘PUF’), and configured to use the PUF to generate a hardware-intrinsic identity representing the physical state of the computing system and to use the PUF as a root-of-trust for the computing system; and

multiple components and an operating system, wherein the computing system is configured to perform a trusted boot procedure starting with verification of the PUF and establishment of a corresponding minimal trust boundary and component-by-component verification following establishment of the minimal trust boundary.

6. The computing system of claim 5 , wherein the PUF is configured to provide intrinsic hardware tamper detection.

7. The computing system of claim 6 , wherein the computing system further comprises one or more software applications and the computing system configured to validate any software application prior to permitting its execution.

8. The computing system of claim 7 , wherein the computing system is configured to store a signed cryptographic hash of any software application upon installation of the software application, the cryptographic hash being signed by the high-assurance processor using the PUF.

9. The computing system of claim 8 , wherein the high assurance processor is configured to, upon requested execution of a software application, compute a cryptographic hash of the software application and validate its signature thereon.

10. The computing system of claim 5 , further including an additional root-of-trust.

11. The computing system of claim 10 , wherein the high-assurance processor is configured to validate the additional root-of-trust after verification of the PUF.

12. The computing system of claim 11 , wherein the additional root-of-trust is a Trusted Platform Module.

13. A computing implemented method for component-by-component verification, the method comprising;

executing, by a high assurance processor having a physical unclonable function (‘PUF’), a trusted boot procedure, wherein executing the trusted boot procedure includes:

verifying a hardware-intrinsic identity representing the physical state of the computing system using the PUF as a root-of-trust for the computing system;

establishing a corresponding minimal trust boundary on the computing system having multiple components and an operating system; and

verifying component-by-component following the act of establishing the minimal trust boundary.

14. The computing implemented method of claim 13 , further comprising providing intrinsic hardware tamper detection by the PUF.

15. The method of claim 13 , further comprising validating an additional root-of-trust, by the high-assurance processor, after verification of the PUF.

16. The method of claim 13 , further comprising validating any software application prior to permitting execution of the software application on the computer system.

17. The method of claim 16 , further comprising signing, by the high-assurance processor using the PUF, a cryptographic hash of the software application upon installation.

18. The method of claim 17 , further comprising computing a cryptographic hash of the software application and validating a signature on the cryptographic hash, responsive to requested execution of a software application.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2017
From: SYPRIS ELECTRONICS, LLC
To: ANALOG DEVICES, INC.
Reel/Frame 041079/0878 →
RELEASE OF SECURITY INTEREST Recorded Sep 15, 2016
From: GREAT ROCK CAPITAL PARTNERS MANAGEMENT, LLC
To: SYPRIS SOLUTIONS, INC.; SYPRIS DATA SYSTEMS, INC.; SYPRIS ELECTRONICS, LLC; SYPRIS TECHNOLOGIES, INC.; SYPRIS TECHNOLOGIES INTERNATIONAL, INC.; SYPRIS TECHNOLOGIES KENTON, INC.; SYPRIS TECHNOLOGIES MARION, LLC; SYPRIS TECHNOLOGIES MEXICAN HOLDINGS, LLC; SYPRIS TECHNOLOGIES NORTHERN, INC.; SYPRIS TECHNOLOGIES SOUTHERN, INC.
Reel/Frame 039759/0328 →
RELEASE OF SECURITY INTEREST Recorded Sep 15, 2016
From: SIENA LENDING GROUP, LLC
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 039759/0348 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2016
From: WALLRABENSTEIN, JOHN ROSS; WALSH, JOHN J.; GARDNER, DOUGLAS J.
To: SYPRIS ELECTRONICS, LLC
Reel/Frame 038430/0665 →
SECURITY AGREEMENT Recorded Nov 5, 2015
From: SYPRIS SOLUTIONS, INC.; SYPRIS DATA SYSTEMS, INC.; SYPRIS ELECTRONICS, LLC; SYPRIS TECHNOLOGIES, INC.; SYPRIS TECHNOLOGIES INTERNATIONAL, INC.; SYPRIS TECHNOLOGIES KENTON, INC.; SYPRIS TECHNOLOGIES MARION, LLC; SYPRIS TECHNOLOGIES MEXICAN HOLDINGS, LLC; SYPRIS TECHNOLOGIES NORTHERN, INC.; SYPRIS TECHNOLOGIES SOUTHERN, INC.
To: GREAT ROCK CAPITAL PARTNERS MANAGEMENT, LLC
Reel/Frame 037055/0796 →