IE type trench gate IGBT
In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.
1. A semiconductor device comprising:
(a) a semiconductor substrate having a first and a second main surfaces;
(b) a drift area disposed in the semiconductor substrate and having a first conductive type;
(c) a cell formation area disposed on the first main surface and having a plurality of trenches arranged in parallel;
(d) a metal gate electrode disposed on the first main surface;
(e) a metal gate wire surrounding the cell formation area and connected to the metal gate electrode;
(f) a metal emitter electrode disposed on the first main surface;
(g) a metal collector electrode disposed on the second main surface;
(h) a collector area disposed between the metal collector electrode and the drift area and having a second conductive type;
(i) a linear active cell having a pair of first and second linear trench gate electrodes and a linear hole collector cell area having a pair of third and fourth linear trench gate electrodes which are disposed alternately on the first main surface;
(j) a body area disposed in a surface area on the side of the first main surface of the drift area and having the second conductive type;
(k) a floating area disposed in the surface area on the side of the first main surface between the linear active cell area and the linear hole collector cell area and having the same conductive type as that of the body area; and
wherein an emitter area of the first conductive type is disposed in the surface area on the side of the first main surface of the body area between the first and the second linear trench gate electrodes, wherein the first and the second linear trench gate electrodes are connected to the metal gate electrode and disposed in first and second trenches in the first main surface,
wherein the third and the fourth linear trench gate electrodes are connected to the metal emitter electrode and disposed in third and fourth trenches in the first main surface, and
wherein a distance from the emitter area disposed on the outer side of the longitudinal direction in the linear active cell area to an edge of the cell formation area is longer than a distance from an edge of the linear hole collector cell area in the longitudinal direction to the edge of the cell formation area in a plan view.
2. The semiconductor device according to claim 1 ,
wherein a width of the first and the second linear trench gate electrodes is narrower than a width of the linear active cell area and the linear hole collector cell area.
3. The semiconductor device according to claim 2 , wherein the emitter area is not disposed in the linear hole collector cell area.
4. The semiconductor device according to claim 3 , wherein a width of the linear active cell area is substantially equal to a width of the linear hole collector cell area.
5. The semiconductor device according to claim 4 , wherein emitter connection parts of the third and the fourth linear trench gate electrodes substantially intersect with contact grooves in contact with the emitter connection parts at right angles.
6. The semiconductor device according to claim 5 , wherein the contact grooves in contact with the emitter connection parts of the third and the fourth linear trench gate electrodes are contained with the emitter connection parts in a plane.