BIOS system with non-volatile data memory

1. A system comprising:

a BIOS system comprising:

a first memory device configured to store data associated with a computer system, wherein the first memory device is a non-volatile random-access memory device;

a second non-volatile memory device configured to store a set of instructions for execution by a processor during initialization of the computer system, wherein the set of instructions comprises at least one instruction configured to read a data value stored in the first memory device;

a controller coupled to the first memory device, the controller configured to manage memory transactions directed to the first memory device, wherein the memory transactions are selected from the group consisting of:

a read from the first memory device; and

a write to the first memory device; and

a third memory device coupled to the controller, wherein the controller is further configured to copy the data stored in the first memory device to the third memory device, the third memory device comprising a dual-port volatile memory device, and the data copied to the third memory device comprising a memory image mirror of the data stored in the first memory device.

2. The system of claim 1 wherein the controller comprises a real time clock (RTC), wherein the controller is configured to communicate a RTC time value to the computer system.

3. The system of claim 2 wherein the controller is further configured to store the real-time clock (RTC) time value in the first memory device on an interruption of electrical power to the computer system.

4. The system of claim 2 wherein the controller communicates the RTC time value to the computer system in response to an RTC read request.

5. The system of claim 1 wherein the controller comprises a device selected from the group consisting of:

a field programmable gate array (FPGA);

an application specific integrated circuit; and

a microcontroller and associated software configured to manage memory transactions to the first memory device.

6. The system of claim 1 further comprising:

a power module coupled to the controller, the first memory, and an electrical power source; and

a capacitor coupled to the power module, the capacitor configured to store electrical energy, wherein the power module is configured to couple the stored electrical energy to the controller and the first memory device if the electrical power source is interrupted.

7. The system of claim 1 further comprising logic coupled to the controller configured to clear the RTC and first memory device in response to a user-initiated command.

8. The system of claim 2 wherein the controller is further configured to:

copy a first time value stored in the first memory device to the third memory device;

copy a first set of data values stored in the first memory device to the third memory device;

if a first value of the first set of data values is changed to a second value, setting the first time value in the first memory device to a second time value from the RTC; and

copy a current set of data values in the third memory device to the first memory device, wherein the current set of data values in the third memory device comprises at least the second value and unchanged values of the first set of data values.

9. The system of claim 1 further comprising a fourth memory device, wherein:

the fourth memory device comprises non-volatile memory device; and wherein

the controller is further configured to copy data in the first memory device and a current time clock value to the fourth memory device.

10. The system of claim 9 wherein the controller is further configured to:

determine if the set of data values in the first memory device is valid, and

copy data stored in the fourth memory device to the first memory device if the set of data values in the first memory device is invalid.

11. The system of claim 10 wherein the controller is further configured to:

determine if the data in the fourth memory device is invalid; and

not copy the data values in the fourth memory device to the first memory device if the data in the fourth memory device is invalid; and

initialize the third memory device with a set of default data.

12. The system of claim 1 wherein the controller further comprises a bus interface coupled to the third memory device.

13. The system of claim 12 wherein the bus interface comprises a Low Pin Count (LPC) bus interface.