Digital-to-analog converter using nonlinear capacitance compensation
View Patent ↗A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.
1. A digital-to-analog converter (DAC) for converting a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal, comprising:
a plurality of DAC current cells, having a plurality of transistors, configured to convert the digital input signal to the analog output signal; and
a compensation module, having a transfer function, coupled to the plurality of transistors,
wherein the transfer function is inversely related to a parasitic capacitance of the plurality of transistors.
2. The DAC of claim 1 , wherein the compensation module comprises:
a first compensation module, having a first plurality of switchable impedances, configured to deactivate one or more of the first plurality of switchable impedances to increase a capacitance of the compensation module; and
a second compensation module, having a second plurality of switchable impedances, configured to deactivate one or more of the second plurality of switchable impedances to decrease the capacitance of the compensation module.
3. The DAC of claim 2 , wherein the first plurality of switchable impedances comprises;
a first plurality of capacitors; and
a first plurality of switching elements, each of the first plurality of switching elements being coupled to a corresponding capacitor from among the first plurality of capacitors, and
wherein the second plurality of switchable impedances comprises:
a second plurality of capacitors; and
a second plurality of switching elements, each of the second plurality of switching elements being coupled to a corresponding capacitor from among the second plurality of capacitors.
4. The DAC of claim 3 , wherein the first plurality of switching elements comprises:
a plurality of n-type metal-oxide-semiconductor transistors (NMOSFETs), each of the plurality of NMOSFETs being coupled to the corresponding capacitor from among the first plurality of capacitors, and
wherein the second compensation module comprises:
a plurality of p-type metal-oxide-semiconductor transistors (PMOSFETs), each of the plurality of PMOSFETs being coupled to the corresponding capacitor from among the second plurality of capacitors.
5. The DAC of claim 1 , wherein the analog output signal is a differential analog output signal including a first analog output signal and a second analog output signal, and
wherein the compensation module comprises:
a first compensation module configured to adjust a linearity of the first analog output signal, and
a second compensation module configured to adjust a linearity of the second analog output signal.
6. The DAC of claim 1 , wherein the compensation module comprises a plurality of switchable impedances,
wherein a first configuration of the plurality of switchable impedances is selected for a first potential difference associated with the parasitic capacitance of the plurality of transistors, and
wherein a second configuration of the plurality of switchable impedances is selected for a second potential difference associated with the parasitic capacitance of the plurality of transistors, the second potential difference being greater than the first potential difference.
7. The DAC of claim 1 , wherein the compensation module is further configured and arranged to be in a parallel configuration with the plurality of transistors.
8. An electronic circuit, comprising:
an integrated circuit that is formed onto a semiconductor substrate using a semiconductor fabrication process, the formation of the integrated circuit onto the semiconductor substrate introducing a parasitic capacitance into the integrated circuit; and
a compensation module, having a transfer function, coupled to the integrated circuit,
wherein the transfer function is inversely related to the parasitic capacitance of the integrated circuit.
9. The electronic circuit of claim 8 , wherein the compensation module comprises:
a first compensation module, having a first plurality of switchable impedances, configured to deactivate one or more of the first plurality of switchable impedances to increase a capacitance of the compensation module; and
a second compensation module, having a second plurality of switchable impedances, configured to deactivate one or more of the second plurality of switchable impedances to decrease the capacitance of the compensation module.
10. The electronic circuit of claim 9 , wherein the first compensation module comprises:
a plurality of n-type metal-oxide-semiconductor transistors (NMOSFETs), each of the plurality of NMOSFETs being coupled to a corresponding switchable impedance from among the first plurality of switchable impedances, and
wherein the second compensation module comprises:
a plurality of p-type metal-oxide-semiconductor transistors (PMOSFETs), each of the plurality of PMOSFETs being coupled to a corresponding switchable impedance from among the second plurality of switchable impedances.
11. The electronic circuit of claim 8 , wherein the compensation module comprises:
a plurality of switchable impedances,
wherein a first configuration of the plurality of switchable impedances is selected for a first potential difference associated with the parasitic capacitance of the integrated circuit, and
wherein a second configuration of the plurality of switchable impedances is selected for a second potential difference associated with the parasitic capacitance of the integrated circuit, the second potential difference being greater than the first potential difference.
12. The electronic circuit of claim 8 , wherein the compensation module is further configured and arranged to be in a parallel configuration with the plurality of transistors.
13. The electronic circuit of claim 8 , wherein the parasitic capacitance of the integrated circuit comprises:
a parasitic gate-to-source capacitance (C GS ) of one or more transistors of the integrated circuit;
a parasitic source-to-bulk capacitance (C SB ) of the one or more transistors;
a parasitic gate-to-drain capacitance (C GD ) of the one or more transistors; or
a parasitic drain-to-bulk capacitance (C DB ) of the one or more transistors.
14. The electronic circuit of claim 8 , wherein the transfer function comprises:
a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitance of the integrated circuit.
15. A compensation module for additively combining with a parasitic capacitance of an integrated circuit, comprising:
a first compensation module, having a first plurality of switchable impedances, configured to deactivate one or more of the first plurality of switchable impedances to increase a capacitance of the compensation module; and
a second compensation module, having a second plurality of switchable impedances, configured to deactivate one or more of the second plurality of switchable impedances to decrease the capacitance of the compensation module.
16. The compensation module of claim 15 , wherein the first compensation module comprises:
a plurality of n-type metal-oxide-semiconductor transistors (NMOSFETs), each of the plurality of NMOSFETs being coupled to a corresponding switchable impedance from among the first plurality of switchable impedances, and
wherein the second compensation module comprises:
a plurality of p-type metal-oxide-semiconductor transistors (PMOSFETs), each of the plurality of PMOSFETs being coupled to a corresponding switchable impedance from among the second plurality of switchable impedances.
17. The compensation module of claim 15 , wherein a first configuration of the first plurality of switchable impedances is selected for a first potential difference associated with the parasitic capacitance of the integrated circuit,
wherein a second configuration of the first plurality of switchable impedances is selected for a second potential difference associated with the parasitic capacitance of the integrated circuit, the second potential difference being greater than the first potential difference, and
wherein a capacitance of the first configuration of the first plurality of switchable impedances is less than a capacitance of the second configuration of the first plurality of switchable impedances.
18. The compensation module of claim 17 , wherein a first configuration of the second plurality of switchable impedances is selected for the first potential difference associated with the parasitic capacitance of the integrated circuit,
wherein a second configuration of the second plurality of switchable impedances is selected for the second potential difference associated with the parasitic capacitance of the integrated circuit, and
wherein a capacitance of the first configuration of the second plurality of switchable impedances is greater than a capacitance of the second configuration of the second plurality of switchable impedances.
19. The compensation module of claim 15 , wherein the compensation module is further configured and arranged to be in a parallel configuration with the integrated circuit.
20. The compensation module of claim 19 , wherein a transfer function of the first and the second compensation modules is inversely related to the parasitic capacitance of the integrated circuit.